Pseudo-dual port memory where ratio of first to second...

Details Pseudo-dual port memory where ratio of first to second... Pseudo-dual port memory where ratio of first to second...

2007-07-31

2007-07-31

Lam, David (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233100, C365S194000

Reexamination Certificate

active

11282333

ABSTRACT:
A pseudo-dual port memory performs both a first memory access operation and a second memory access operation in a single period of an externally supplied clock signal CLK. The signal CLK is used to latch a first address for the first operation and a second address for the second operation. Control circuitry generates first control signals that initiate the first operation. The time duration of the first operation depends upon a delay through a delay circuit. A precharge period follows termination of the first operation. The time duration of the precharge period depends upon a propagation delay through the control circuit. The memory access of the second operation is initiated following termination of the precharging. The time duration of the second memory access depends on a delay through the delay circuit. The time when the second operation is initiated is independent of the duty cycle of CLK.

REFERENCES:
patent: 5768213 (1998-06-01), Jung et al.
patent: 6882562 (2005-04-01), Beucler

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