Pseudo-static synchronous semiconductor memory device

Details Pseudo-static synchronous semiconductor memory device Pseudo-static synchronous semiconductor memory device

2005-03-01

2005-03-01

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233500, C365S230010

Reexamination Certificate

active

06862247

ABSTRACT:
For a pseudo-SRAM (Static Random Access Memory) macro operating in synchronization with a clock signal, a page operation instructing signal instructing a page operation and a page close instructing signal instructing completion of the page operation are prepared as control signals designating operation modes. A pseudo-SRAM can be selectively operated in a page mode in accordance with the page operation instructing signal and the page close instructing signal, and an operation of row-related circuitry in each clock cycle can be inhibited so that an average power consumption can be reduced. The power consumption of the pseudo-SRAM can be reduced without lowering an operation speed.

REFERENCES:
patent: 5513327 (1996-04-01), Farmwald et al.
patent: 6714479 (2004-03-01), Takahashi et al.
patent: 2-87399 (1990-03-01), None

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