Pseudo SRAM having combined synchronous and asynchronous...

Details Pseudo SRAM having combined synchronous and asynchronous... Pseudo SRAM having combined synchronous and asynchronous...

2006-10-10

2006-10-10

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230080

Reexamination Certificate

active

07120085

ABSTRACT:
A PSRAM features a mode register set (MRS) for setting a mode register at a combined synchronous and asynchronous mode. The PSRAM having a combined synchronous and asynchronous mode register set includes a MRS, a mode register control unit, a plurality of control signal buffers, an address buffer, a clock buffer, and a synchronous and asynchronous detecting unit. Here, the plurality of control signal buffers, the address buffer and the clock buffers are controlled by a chip selecting signal at an asynchronous mode, and are operated synchronously with respect to an internal clock outputted from the clock buffer regardless of the chip selecting signal at a synchronous mode.

REFERENCES:
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patent: 6026465 (2000-02-01), Mills et al.
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patent: 6697296 (2004-02-01), Matsumoto et al.
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patent: 09-237197 (1997-09-01), None
patent: 2000-268564 (2000-09-01), None

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