Static information storage and retrieval – Addressing – Sync/clocking
Patent
1994-05-03
1997-08-26
Nguyen, Viet Q.
Static information storage and retrieval
Addressing
Sync/clocking
365233, 365194, 365193, 365195, G11C 800
Patent
active
056616945
ABSTRACT:
A semiconductor memory device is provided with terminals for receiving a chip enable signal and an address signal, an internal circuit, and an internal control signal generating circuit for generating a predetermined internal control signal which makes an output timing of the semiconductor memory device same regardless of a level of the address signal when the chip enable signal undergoes a transition from an inactive level to an active level. The internal circuit is deactivated in response to the inactive level of the chip enable signal and is activated in response to the active level of the chip enable signal.
REFERENCES:
patent: 4858197 (1989-08-01), Aono et al.
patent: 5243575 (1993-09-01), Sambandan et al.
Fujieda Waichiro
Fujii Atsushi
Fujimoto Hiroyuki
Fukutani Yutaka
Hirayama Seizi
Fujitsu Limited
Nguyen Viet Q.
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