Precharge control signal generator, and semiconductor memory...

Details Precharge control signal generator, and semiconductor memory... Precharge control signal generator, and semiconductor memory...

2003-01-21

2003-11-04

Mai, Son (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S201000, C365S203000

Reexamination Certificate

active

06643218

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a synchronous memory device, and in particular to an improved synchronous memory device having an asynchronous precharge function which can input an interval between commands regardless of a clock period. It accomplishes this by generating a precharge control signal asynchronous with respect to a clock signal by using a clock enable signal or chip selector bar signal which is not synchronous with the clock signal.
2. Description of the Background Art
A conventional synchronous DRAM will now be explained with reference to
FIGS. 1 through 5
.
FIG. 1
(Prior Art) is a block diagram illustrating a conventional synchronous memory device. The conventional synchronous DRAM includes a command buffer
20
receiving external commands such as a clock signal CLK, a chip selector signal /CS, a ras bar signal /RAS, a cas bar signal /CAS and a write bar signal /WE; an address buffer
22
receiving external addresses A
0
-Ai; and a data IN/OUT buffer
24
receiving and outputting data signals DQ
0
-DQj.
The conventional synchronous DRAM also includes a command decoder
26
receiving the output signals /CSI, /RASI, /CASI, /WEI from the command buffer
20
, and generating a precharge control signal PREI for controlling the internal operation, a write signal W, an active signal ACT, a read signal R and a mode selection signal MS. A mode register
28
receives the output signal from the address buffer
22
and the mode selection signal MS from the command decoder
26
, and controls an operation mode. A test mode detector
34
receives the address signal A
0
and the output signal from the mode register
28
, and generates a test mode detection signal TEST. A precharge control signal generator
60
comprising a TPRE signal generator
36
receives the write signal W from the command decoder
26
, the write enable signal /WEI from the command buffer
20
, and the detection signal TEST from the test mode detector
34
, and generates a test mode precharge control signal TPRE. An OR gate
38
ORs the precharge control signal PREI from the command decoder
26
and the TPRE signal from the TPRE signal generator
36
, and generates a precharge control signal PRE.
In addition, the conventional synchronous DRAM includes a column address latch unit
30
latching the column address signal from the address buffer
22
, and generating a column address latch signal CA. A column decoder
40
decodes the column address latch signal CA from the column address latch unit
30
, and selects a bit line of a memory cell array unit
50
. A row address latch unit
32
receives the address signal from the address buffer
22
, and generates a row address latch signal RA. A row decoder
42
decodes the row address latch signal RA from the row address latch unit
32
, and selects a word line of the memory cell array unit
50
.
The conventional synchronous DRAM includes a precharge/equalize unit
44
precharging and equalizing a bit line potential of the memory cell array unit
50
into half a potential ½Vcc according to the precharge control signal PRE from the OR gate
38
, when data are not written/read to/from the memory cell array
50
. A sense amplifier unit
46
precharges and equalizes the bit line potential into half a potential ½Vcc according to the precharge control signal PREI, when data are not written/read to/from the memory cell array
50
, and amplifies data of the bit line, when data are written/read to/from the memory cell array
50
. I/O unit
48
connects the data inputted/outputted through the data IN/OUT buffer
24
to the sense amplifier unit
46
.
FIG. 2
(Prior Art) is a block diagram of a conventional synchronous memory array. The memory array includes a memory cell
56
comprising one NMOS transistor N and one capacitor Cs. One terminal of the capacitor Cs is connected to the NMOS transistor N through a resistor Rc, and the other terminal is supplied with cell plate voltage VPLT. If an word line WL is selected according to an address signal and then sense amplifier enable signal SAEN is activated, a sense amplifier
53
amplifies data of the bit line BL and bit bar line /BL. Switch circuit units
51
and
52
switch the I/O lines IO, /IO and bit lines BL, /BL according to a column decoder signal Y_sw. An equalizing circuit
54
equalizes the bit lines BL, /BL according to an equalize signal EQ. A division circuit
55
divides the bit lines BL, /BL according to a control signal ISO.
FIG. 3
(Prior Art) is a timing diagram of an array operation of the conventional synchronous memory device. The operation of the conventional synchronous memory device is controlled according to a command signal CMD synchronous with an external clock signal CLK. In the command signal CMD, ACT means active command, WT means write command, RD means read command, and PRE means precharge command. In
FIG. 3
, SAEN is a sense amplifier enable signal, BL and /BL are bit line signals, CELL is a voltage signal of a memory cell, Y_sw is a column decoder signal. And in
FIG. 3
, VDD indicates power supply voltage, VPP indicates high voltage, and VSS indicates substrate voltage.
Firstly, the memory array is controlled in an active state according to the active command ACT (ACTIVE_STATE=high), a specific word line is selected according to the row address (Word Line=VDD~VPP), and thus a data of the memory cell is applied to the bit line BL and the bit bar line /BL according to charge sharing. Here, the bit line BL and the bit bar line /BL have a small potential difference due to a capacitance ratio between the memory cell and the bit line, which is sensed to a wanted potential by the operation of the sense amplifier (SAEN=high).
Thereafter, when a column command signal R or W is externally inputted, data can be inputted to the memory device and outputted from the memory device through a date in/out pin(not shown in the figures) according to the operation of the data IN/OUT buffer
24
, the sense amplifier unit
46
and the I/O unit
48
. At this time, if a succeeding column command is the write command W and the inputted data is different from the data stored in the memory array, the bit line BL, the bit bar line /BL and the memory cell renew data of the memory cell according to the operation indicated by a dotted line of FIG.
3
. The data of the memory cell are renewed later than the data of the bit line BL and the bit bar line /BL. Such a delay is generated by a parasitic resistance element such as a transistor and a contact hole of the memory cell due to integration of the memory device.
After the column operation of the write and read operation, a data storage state of the memory cell is normally maintained and the precharge control signal PRE is applied to perform a succeeding row access operation. When the precharge control signal PRE is inputted, the data of the memory cell are maintained, the word line, the sense amplifier enable signal SAEN, the bit line BL and the bit bar line /BL are sequentially disabled, and the memory device is prepared to perform the succeeding row access operation. As described above, the operation of the conventional synchronous memory device is performed according to the command CMD synchronous with clock signal CLK.
FIG. 4
(Prior Art) is a timing diagram of the write operation of the conventional synchronous memory device. When the active command signal ACT synchronous with a rising period of clock signal CLK is inputted, the memory array is controlled in an active state (ACTIVE_STATE=high). Thereafter, when a write command signal WT is inputted in the active state of the memory array (ACTIVE_STATE=high), a series of operations are performed to input a write data through a DQ pin and store the data in the memory array. When the precharge control signal PRE is inputted, the active state signal ACTIVE_state of the memory array enabled in a high level is disabled in a low level. Accordingly, in the write operation of the conventional synchronous memory device, the

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