Protection circuit to ensure DRAM signal in write cycle

Details Protection circuit to ensure DRAM signal in write cycle Protection circuit to ensure DRAM signal in write cycle

1999-04-12

2000-05-02

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Sync/clocking

365203, G11C 700

Patent

active

060580690

ABSTRACT:
Methods are disclosed for a dynamic random access memory (DRAM) which ensure that the last write operation in a DRAM column cycle is not turned off before the bit line restore is completed, thus avoiding that data is destroyed in the next access. In addition these methods allow the precharge command to occur before the write data are fully restored. This is achieved by a providing a TWR Protect Circuit which adds a Timing Reference and Timing Compare circuit to the DRAM control logic, such that a last write cycle out of `n` cycles is recognized and that the bit line restore period of the that last write cycle is extended to ensure that bit line BL and BLB reach full voltage.

REFERENCES:
patent: 4998222 (1991-03-01), Sussman
patent: 5404327 (1995-04-01), Houston
patent: 5703832 (1997-12-01), Ting et al.
patent: 5877988 (1999-03-01), Shim et al.

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