Phase locked loop circuit and method of locking a phase

Details Phase locked loop circuit and method of locking a phase Phase locked loop circuit and method of locking a phase

2006-05-09

2008-09-02

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C327S156000

Reexamination Certificate

active

07420870

ABSTRACT:
A phase locked loop circuit and method of locking a phase. The phased locked loop circuit may include a phase detector receiving an external clock signal and a feedback clock signal and outputting an up signal when a phase of the external clock signal leads a phase of the feedback clock signal and outputting a down signal when the phase of the external clock signal lags the phase of the feedback clock signal, a loop filter circuit increasing a control voltage in response to the up signal and decreasing the control voltage in response to the down signal, and a voltage controlled oscillator circuit receiving the control voltage and directly generating at least n (where n is an integer ≧4) internal clock signals. The phased locked loop circuit may also include a voltage controlled oscillator circuit, including at least four loops, receiving the control voltage and generating multiple internal clock signals.

REFERENCES:
patent: 4380742 (1983-04-01), Hart
patent: 5250914 (1993-10-01), Kondo
patent: 5592126 (1997-01-01), Boudewijns et al.
patent: 6008680 (1999-12-01), Kyles et al.
patent: 6075419 (2000-06-01), Sun et al.
patent: 6100768 (2000-08-01), Hirayama
patent: 6137369 (2000-10-01), Kermani
patent: 6181210 (2001-01-01), Wakayama
patent: 6304113 (2001-10-01), Dautriche
patent: 6329882 (2001-12-01), Fayneh et al.
patent: 6456165 (2002-09-01), Kelkar
patent: 6504438 (2003-01-01), Li et al.
patent: 6570423 (2003-05-01), Trivedi et al.
patent: 6611161 (2003-08-01), Kumar et al.
patent: 6650594 (2003-11-01), Lee et al.
patent: 6815990 (2004-11-01), Lee
patent: 6968356 (2005-11-01), Lakhdir
patent: 2003/0198311 (2003-10-01), Song et al.
patent: 2005/0057316 (2005-03-01), Kim
patent: 8-316802 (1996-11-01), None
patent: WO 2004/017518 (2004-02-01), None
Kuo-Hsing Cheng et al. “A Difference Detector PFD for Low Jitter PLL”. ICECS 2001. The 8th IEEE International Conference Electronics, Circuits and Systems, 2001. On pp. 43-46 vol. 1 ISBN: 0-7803-7057-0. Meeting Date: Sep. 2-5, 2001.
Salvatore Levantino, et al., Phase Noise in Digital Frequency Dividers,IEEE Journal of Solid State Circuits vol. 39, No. 5, pp. 775-784.
Chun-Huat Heng and Bang-Sup Song, A 1.8 GHz CMOS fractional-N frequency synthesizer with randomized multi-phase VCO. This paper appears in: Proceedings of the IEEE 2002 Custom Integrated Circuits Conference. Publication Date: 2002 On pp. 427-430. Meeting Date: May 12-15, 2002.
Lizhong Sun, Kwasniewski, T., and Iniewski, K., A quadrature output voltage controlled ring oscillator based on three-stage sub-feedback loops, This paper appears in: Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, 1999. ISCAS '99. Publication Date: Jul. 1999, vol. 2, On pp. 176-179 vol. 2.
German Office Action dated Aug. 3, 2005.

Affiliated with

Also associated with

Rating

Phase locked loop circuit and method of locking a phase does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Phase locked loop circuit and method of locking a phase, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase locked loop circuit and method of locking a phase will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3971007