Phase controlled high speed interfaces

Details Phase controlled high speed interfaces Phase controlled high speed interfaces

2005-12-13

2005-12-13

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S193000, C365S194000

Reexamination Certificate

active

06975557

ABSTRACT:
A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

REFERENCES:
patent: 5485490 (1996-01-01), Leung et al.
patent: 6707728 (2004-03-01), Lee
patent: 6822924 (2004-11-01), Lee
patent: 2001/0025350 (2001-09-01), Hohler et al.
patent: 2003/0035502 (2003-02-01), Boerker
European Search Report, dated Jan. 18, 2005, for European Patent Appl. No. 04023594.7, 3 pages.

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