Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2008-02-19
2010-11-16
Le, Vu A (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S233110
Reexamination Certificate
active
07835220
ABSTRACT:
A PLL circuit includes a phase comparator for outputting a frequency control signal based on a result of comparison between phases of an input reference clock signal and a fed-back oscillation signal; an oscillation circuit, connected to the phase comparator, for outputting an oscillation signal having a frequency in accordance with the frequency control signal, a power source voltage, and a predetermined reference voltage; and a bias control circuit, connected to the oscillation circuit, for increasing either the potential difference between the reference voltage of the oscillation circuit and a ground voltage or the potential difference between the power source voltage of the oscillation circuit and the ground voltage. A transistor in the oscillation circuit can operate in a saturation area, thereby operating the PLL circuit at a high speed with a low power source voltage, without being easily affected by a variation in the temperature or other process conditions.
REFERENCES:
patent: 6667663 (2003-12-01), Ozawa
patent: 2003/0011437 (2003-01-01), Ozawa
patent: 2004/0239386 (2004-12-01), Lim et al.
patent: 2008/0191761 (2008-08-01), Ikeda et al.
patent: H8-130465 (1996-05-01), None
Elpida Memory Inc.
Le Vu A
Sughrue & Mion, PLLC
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