Phase shift correction circuit for monolithic random access memo

Details Phase shift correction circuit for monolithic random access memo Phase shift correction circuit for monolithic random access memo

1995-04-19

1996-08-27

Dinh, Son

Static information storage and retrieval

Addressing

Sync/clocking

36518907, 365194, 327158, 327277, G11C 800

Patent

active

055507832

ABSTRACT:
A synchronous burst SRAM (110) is disclosed that includes a clock circuit (112) having a phase correction subcircuit (134) and a clock routing subcircuit (132). The clock routing subcircuit (132) provides an internal clock signal to at least one clocked circuit. The phase correction subcircuit (134) is a modified phase locked loop that includes a phase comparator (138) that receives an external clock signal and a delayed internal clock signal. In response to the signals, the phase comparator (138) provides a phase error signal to a charge pump (140) which is coupled to a loop filter (142) to provide an error voltage. The error voltage is coupled to a VCO (144) which provides the internal clock signal as an output. The internal clock signal is coupled to the input of the phase comparator (138) by a feedback circuit which generates the delayed internal clock signal for the phase comparator (138). The feedback circuit can include a number of delay elements (146) to simulate the clock delay inherent in the clock routing subcircuit (132) so that the resulting internal clock signal is phase shifted to compensate for delays caused by the clock routing subcircuit (132).

REFERENCES:
patent: 4970693 (1990-11-01), Nozaki et al.
patent: 5440514 (1995-08-01), Flannagan et al.
patent: 5440515 (1995-08-01), Chang et al.
patent: 5444667 (1995-08-01), Obara

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