Parallel data path architecture

Details Parallel data path architecture Parallel data path architecture

2007-07-17

2007-07-17

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S221000

Reexamination Certificate

active

11157868

ABSTRACT:
A memory device includes: a memory array for storing data; data pads for supplying as an output of the memory device data retrieved from the memory array in a read operation; parallel read data paths each coupled between the memory array and the data pads, where the parallel read data paths include synchronous data paths operable in different modes of operation and an asynchronous data path; and a mode selector for selecting one of the parallel read data paths to supply data retrieved from the memory array to the data pads.

REFERENCES:
patent: 5867446 (1999-02-01), Konishi et al.
patent: 6754132 (2004-06-01), Kyung
patent: 6901026 (2005-05-01), Takeuchi et al.
patent: 2005/0169091 (2005-08-01), Miki et al.
patent: 2006/0179260 (2006-08-01), Yoon

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