Pipelined dual port RAM

Static information storage and retrieval – Addressing – Sync/clocking

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Details

36518902, 36518905, 36523002, 36523005, 340703, G11C 704

Patent

active

052068331

ABSTRACT:
A pipelined random access memory for use in color display system. A multiplexer, including a video port and a microprocessor port, provides the RAM input. A memory array, a sensing latch and an I/O latch, in addition to the multiplexer, provide the pipeline architecture, enabling the random memory to be accessed at three different locations simultaneously. Thus, with the same memory speed, the data throughput of this RAM is triple that in the known art. A clock circuit is constructed to generate extremely stable internal clock pulses so that the interval of each clock pulse varies automatically according to the IC manufacturing process and the ambient temperature in use, thereby adapting to the appropriate precharging interval related to the memory array, multiplexer, and sensing latch.

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