Pipelined dual port RAM

Details Pipelined dual port RAM Pipelined dual port RAM

1991-03-13

1993-04-27

Heyman, John S.

Static information storage and retrieval

Addressing

Sync/clocking

36518902, 36518905, 36523002, 36523005, 340703, G11C 704

Patent

active

052068331

ABSTRACT:
A pipelined random access memory for use in color display system. A multiplexer, including a video port and a microprocessor port, provides the RAM input. A memory array, a sensing latch and an I/O latch, in addition to the multiplexer, provide the pipeline architecture, enabling the random memory to be accessed at three different locations simultaneously. Thus, with the same memory speed, the data throughput of this RAM is triple that in the known art. A clock circuit is constructed to generate extremely stable internal clock pulses so that the interval of each clock pulse varies automatically according to the IC manufacturing process and the ambient temperature in use, thereby adapting to the appropriate precharging interval related to the memory array, multiplexer, and sensing latch.

REFERENCES:
patent: 4484187 (1984-11-01), Brown et al.
patent: 4503490 (1985-03-01), Thompson
patent: 4506348 (1985-03-01), Miller et al.
patent: 4511965 (1985-04-01), Rajaram
patent: 4719601 (1988-01-01), Gray et al.
patent: 4804948 (1989-02-01), Nishi et al.
patent: 4825390 (1989-04-01), Van Aken et al.
patent: 4882709 (1989-11-01), Wyland
patent: 4970693 (1990-11-01), Nozaki et al.

Affiliated with

Also associated with

Rating

Pipelined dual port RAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pipelined dual port RAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pipelined dual port RAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2333163