Power savings for memory arrays

Details Power savings for memory arrays Power savings for memory arrays

1998-12-22

1999-11-16

Phan, Trong

Static information storage and retrieval

Addressing

Sync/clocking

36523003, 36523006, G11C 800

Patent

active

059869690

ABSTRACT:
Power usage of an integrated circuit including an embedded memory array is reduced significantly by preventing a clock signal from clocking unaccessed memory blocks in the embedded memory array while allowing the clock signal to clock the currently accessed memory block. In an exemplary embodiment, the clock signal is gated with individual memory block enable signals such that the clock signal clocks only the currently enabled or accessed memory block. Only one memory block or a limited number of memory blocks out of an array of memory blocks on a data bus is clocked or operated at any one time. In another embodiment, a delay circuit delays the removal of the clock signal to the accessed memory block until a period of time after the enable signal to the memory block is removed. Thus, the accessed or enabled memory block is allowed to clock internally substantially only during a time corresponding to when that memory block is enabled or accessed.

REFERENCES:
patent: 5477491 (1995-12-01), Shirai
patent: 5666322 (1997-09-01), Conkle
patent: 5708622 (1998-01-01), Ohtani et al.
patent: 5805514 (1998-09-01), Iwakiri
patent: 5808958 (1998-09-01), Vogley et al.
patent: 5872742 (1999-02-01), Kengeri et al.

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