Phase-locked loop timing controller in an integrated circuit mem

Details Phase-locked loop timing controller in an integrated circuit mem Phase-locked loop timing controller in an integrated circuit mem

1995-09-21

1997-09-09

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

365194, 36523003, 327147, G11C 800

Patent

active

056663226

ABSTRACT:
Interleaved operation of multiple memory banks is improved by including a frequency multiplier and a synchronizing circuit, such as a phase-locked loop, as part of an integrated circuit memory chip. Frequency multiplication supplies additional clock edges for timing different phases of the system clock signal. The synchronizing circuit provide precise control of clock edge timing to exactly align the timing signals in one memory chip with the timing signals in another memory chip despite variability in temperature, process and voltage parameters between the chips.

REFERENCES:
patent: 4654864 (1987-03-01), Ichiyoshi
patent: 5440515 (1995-08-01), Chang et al.
patent: 5452324 (1995-09-01), Lewis et al.
patent: 5475718 (1995-12-01), Rosenkranz
patent: 5539344 (1996-07-01), Hatakenaka

Affiliated with

Also associated with

Rating

Phase-locked loop timing controller in an integrated circuit mem does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Phase-locked loop timing controller in an integrated circuit mem, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase-locked loop timing controller in an integrated circuit mem will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-74182