DDR synchronous flash memory with virtual segment architecture
DDR synchronous flash memory with virtual segment architecture
Decoder arrangement of a memory cell array
Decoding circuit and method for functional block selection
Decoding hierarchical architecture for high integration memories
Device and method for isolating bit lines from a data line
Device for writing data into memory and method thereof
Digital memory circuit having a plurality of memory banks
Digital memory circuit having a plurality of segmented...
Direct memory swapping between NAND flash and SRAM with...
Distributed array activation arrangement
Distribution of bank accesses in a multiple bank DRAM used...
Divided word line architecture for embedded memories using multi
Dram active termination control
DRAM architecture with combined sense amplifier pitch
DRAM array interchangeable between single-cell and twin-cell...
Dram bit line selection circuit for selecting multiple pairs of
DRAM core refresh with reduced spike current
Dram core refresh with reduced spike current
DRAM having a reduced chip size