Decoder arrangement of a memory cell array

Details Decoder arrangement of a memory cell array Decoder arrangement of a memory cell array

2006-10-17

2006-10-17

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060

Reexamination Certificate

active

07123537

ABSTRACT:
A hybrid memory cell array including a preferable arrangement of a row decoder is proposed, and in the same manner of addressing a memory cell in the memory array a high access speed of the memory cell and high integration layout of a memory chip can be achieved. A hybrid memory cell includes a plurality of memory cells that each includes an electronic circuit to store binary logic values, a plurality of word lines, a plurality of bit lines, a row decoder arranged in the memory cell array to enable the plurality of word lines and select a memory cell on a same word line, and a column decoder arranged outside the memory cell array to enable the plurality of bit lines and select a memory cell on a same bit line.

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