Dram core refresh with reduced spike current

Details Dram core refresh with reduced spike current Dram core refresh with reduced spike current

1998-10-09

2000-06-13

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

365222, G11C 800

Patent

active

060757442

ABSTRACT:
A method for reducing the communication overhead over the interface bus to the memory devices for refresh operations. This is done by refreshing multiple banks in response to a single command. Multibank refresh is made possible by varying the current profile for the row sense and row precharge currents during a refresh operation, as compared to normal memory access. Unlike normal memory accesses, data is not needed, and a fast access time is not required. This allows the current to be spread using different circuitry for driving the current to lessen current spikes. The spread current is still maintained within the timing of a normal memory access.

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patent: 5726943 (1998-03-01), Yamagata et al.
patent: 5774409 (1998-06-01), Yamazaki et al.

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