Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2000-11-09
2002-05-28
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230040, C365S189011
Reexamination Certificate
active
06396763
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a DRAM having a reduced chip size and, more particularly, to an improvement of the layout of memory cell banks in a DRAM.
(b) Description of a Related Art
It is desired that semiconductor memory devices such as DRAM operate in a higher speed with improved performances in accordance with the higher speed and the improved performances of associated microprocessors. The current techniques for improving the performances of the DRAMs include a synchronous operation technique wherein the internal timings of the DRAM (SDRAM) is controlled in synchrony with a system clock, a multi-bank technique wherein the memory cells are separated into a plurality of banks each operating independently of one another, and a uniform timing technique wherein the layout of memory cells is designed so that the propagation delays of read-write data are equalized by reducing the difference between the line lengths of the signal lines, i.e., I/O bus lines from the bonding pads (external terminals) of the DRAM to the I/O terminals (internal terminals) of the banks of the memory cells.
FIG. 1
shows the layout of a SDRAM arranged in accordance with the uniform timing layout technique such as described in Patent Publication JP-A-
11-97633
. The SDRAM has four banks including a bank A having a pair of memory cell plates
61
and
62
, a bank B having a pair of memory cell plates
63
and
64
, a bank C having a pair of memory cell plates
65
and
66
, and a bank D having a pair of memory cell plates
67
and
68
. The SDRAM also includes a plurality of amplifying sections each including a plurality of input/output amplifiers
72
for inputting/outputting data to/from each of the banks A to D and sixteen bonding pads
71
disposed at a specified location of the SDRAM.
Each of the memory cell plates
61
to
68
includes eight I/O terminals
73
. A pair of memory cell plates, for example, memory cell plates
61
and
62
, in each bank is juxtaposed to form a bank. When a bank is selected among the four banks by an input address in a read/write operation, the pair of memory cell plates in the bank are activated at a time, whereby sixteen memory cells in the memory cell plates of the bank are selected to deliver 16-bit data through the bonding pads
71
.
The bonding pads
71
include two groups of bonding pads
71
including a first group allocated with sequential numbers
0
16
(hexadecimal notation) to
7
16
in an ascending order, and a second group allocated with sequential numbers F
16
to
8
16
in a descending order. All the bonding pads
71
are arranged in a row by a shift allocation technique wherein the bonding pads #
0
to #
7
in the first group and the bonding pads #F to #
8
in the second groups are arranged alternately to form an array of the bonding pads
71
. The I/O terminals
73
for each of the banks A to D are also arranged in a shift allocation technique similarly to the bonding pads
71
, as illustrated in FIG.
1
. The location of the bonding pads
71
is determined near the left side of the chip based on the JDEC standard.
In the DRAM as described above, the shift allocation technique used for arranging the bonding pads
71
and the I/O terminals
73
of the memory cell plates
61
to
68
allows a substantially equal length for the line lengths of the I/O bus lines
74
as viewed from the I/O terminals
73
to the respective bonding pads
71
. The shift allocation technique for the I/O terminals
73
, however, causes a large restriction on the arrangement of the memory cells in the memory cell plates
61
to
68
, whereby the design choice for the arrangement in each bank is strictly restricted. In addition, the large number of I/O amplifiers
72
used in the DRAM, which is equal to the number of I/O terminals
73
of all the banks, increases the occupied area of the DRAM chip.
SUMMARY OF THE INVENTION
In view of the above it is an object of the present invention to provide a SDRAM having a reduced chip size by reducing the number of I/O amplifiers of the DRAM.
The present invention provides a semiconductor memory device including a pair of memory cell banks each capable of being activated when the other of the pair of the memory cell banks is inactivated, an I/O amplifier section including a plurality of I/O amplifiers and disposed for the pair of memory cell banks, the I/O amplifier section amplifying read/write data from/to one of the pair of memory cell banks during activation thereof.
In accordance with the semiconductor memory device of the present invention, since two banks are not activated at a time, the common I/O amplifiers shared by a pair of banks can operate for each of the banks separately. This reduces the number of the I/O amplifiers disposed in the semiconductor memory device, thereby reducing the occupied area for the semiconductor memory device.
In one embodiment of the present invention, each of the banks includes two memory cell plates or more, and each of the memory cell plates in one of the banks is juxtaposed with a corresponding one of another of the banks to form a memory cell plate pair, thereby forming the pair of banks.
The term “memory cell plate” as used herein means a block of memory cells in a memory cell bank, which includes a plurality of memory cell plates activated at a time for delivering a set of read data or receiving a set of write data. The term “memory cell plate pair” as used herein means two memory cell plates which are juxtaposed to share common I/O amplifiers and common I/O bus lines based on the present invention.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.
REFERENCES:
patent: 5973991 (1999-10-01), Tsuchida et al.
patent: 6023437 (2000-02-01), Lee
patent: 6088283 (2000-07-01), Hayashi
patent: 6201744 (2001-03-01), Takashi
patent: 411144464 (1999-05-01), None
patent: 1197633 (1999-09-01), None
Lam David
Nelms David
Young & Thompson
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