Divided word line architecture for embedded memories using multi

Details Divided word line architecture for embedded memories using multi Divided word line architecture for embedded memories using multi

1998-03-30

1999-08-03

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

36518908, 36518911, 36523008, G11C 800

Patent

active

059333871

ABSTRACT:
A semiconductor memory architecture is disclosed which results in reduced power dissipation. This reduction is accomplished by partitioning the word line of an array into segments thereby forming selectable blocks within the array. The power is reduced by the number of blocks by which the array can be partitioned. The word line segments are routed to a central decoder with a block select provision. Routing is accomplished with interconnect lines which are typically metal layers. The array remains continuous in spite of block partitioning.

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