Dram bit line selection circuit for selecting multiple pairs of

Details Dram bit line selection circuit for selecting multiple pairs of Dram bit line selection circuit for selecting multiple pairs of

1996-10-28

1998-06-30

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

36518911, 365207, 365208, G11C 800

Patent

active

057744076

ABSTRACT:
A DRAM bit line selection circuit for selecting multiple pairs of bit lines connecting a bidirectional sense amplifier and a cell array having at least two blocks, the bit line selection circuit includes a block selecting circuit for receiving block selection coding signals corresponding to each block, generating a first signal corresponding to a selected block and a second signal corresponding to a non-selected block, and maintaining the first signal and the second signal until a non-selected block is selected; a level transition unit for outputting a transition signal having one of a first level and a second level in response to an output from the block selecting circuit; and a bit line selecting signal generating unit for generating a bit line selecting signal in response to the transition signal of the level transition unit, wherein the bit line selecting signal corresponding to the selected block maintains the first level, and changes to a third level when the non-selected block is selected.

REFERENCES:
patent: 5267214 (1993-11-01), Fujishima et al.
patent: 5361233 (1994-11-01), Kotani
patent: 5473576 (1995-12-01), Matsui
patent: 5477498 (1995-12-01), Ooishi
patent: 5640363 (1997-06-01), Furutani et al.

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