DDR synchronous flash memory with virtual segment architecture

Details DDR synchronous flash memory with virtual segment architecture DDR synchronous flash memory with virtual segment architecture

2005-01-18

2005-01-18

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230080, C365S230090, C365S233100, C365S185110, C365S185330

Reexamination Certificate

active

06845057

ABSTRACT:
An improved memory device and architecture has been detailed that enhances a Flash memory device that has an SDRAM compatible interface. The memory device employs a virtual paging scheme that allows for the architecture of the memory to implement an efficient Flash memory structure internally. Externally, the memory logically maps the internal Flash architecture to an SDRAM compatible interface and virtual architecture, allowing for memory access and operation with a compatible SDRAM controller device. A double data rate interface is provided to allow data to be input and output from the memory in synchronization with both rising and falling edges of a clock signal.

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