Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1996-01-19
1997-11-25
Popek, Joseph A.
Static information storage and retrieval
Addressing
Plural blocks or banks
36523006, G11C 700
Patent
active
056919506
ABSTRACT:
A memory device includes an address decoder, a global data line, and a plurality of memory blocks, which are each coupled to the address decoder and the global data line. Each memory block includes a plurality of column lines, a local data line, and a plurality of memory cells that are arranged in columns and are each coupled to a corresponding one of the column lines. Each memory block also includes or has associated therewith a switching circuit that is coupled to the column lines and the local data line. The switching circuit couples a selected column line to the local data line and couples the local data line to the global data line when the memory block is selected. The switching circuit uncouples each of the column lines from the local data line when the memory block is unselected, or during a read cycle when the memory block is selected and the sense-amplifier is enabled.
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Carlson David V.
Galanthay Theodore E.
Jorgenson Lisa K.
Popek Joseph A.
SGS-Thomson Microelectronics Inc.
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