Digital memory circuit having a plurality of memory banks

Details Digital memory circuit having a plurality of memory banks Digital memory circuit having a plurality of memory banks

2006-06-20

2006-06-20

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230030, C714S710000

Reexamination Certificate

active

07064999

ABSTRACT:
A digital memory circuit has at least two pairs of adjacent memory banks. Each of the banks has n parallel terminals for n read/write data lines. Each bank pair has only two bundles of n/2 read/write data lines. A first bundle is assigned to the first half of a first bank and to a second half of a second bank and the second bundle is assigned to a second half of the first bank and to a first half of the second bank. Data are input/output in parallel to n/2 input/output lines with the timing of successive half-periods of a clock signal. A changeover device is changeable between different switching states for connecting a bundle of n/2 input/output lines to the read/write data lines of the bank pair containing the addressed bank, depending on whether the data are assigned to the first or second half-period of the clock signal.

REFERENCES:
patent: 4482984 (1984-11-01), Oritani
patent: 6337830 (2002-01-01), Faue
patent: 2001/0034819 (2001-10-01), Nicosia et al.

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