Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2002-10-07
2004-03-23
Tran, Michael (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S191000
Reexamination Certificate
active
06711085
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a digital memory circuit that contains at least two areas each having a multiplicity of memory cells, disposed in matrix form in rows and columns, for storing in each case a binary datum. For each column, a primary sense amplifier is provided to sense the datum stored in an addressed cell. A transfer switch, which can be closed by a column selection signal, is provided to put the first core of a two-core local data line, assigned to the relevant primary sense amplifier, at a first logic potential and the second core of the data line at a second logic potential, if the sensed datum has the first binary value, and to put the first core at the second logic potential and the second core at the first logic potential, if the sensed datum has the second binary value. The cores of each local data line are connected via a respective line switch, which can be closed by a line switch through-connect command, to the cores of an assigned two-core master data line, which leads to the input terminals of an individually assigned secondary sense amplifier. Precharge devices are provided in order, prior to a line switch through-connect command, to equalize both cores of all the local data lines to a potential lying between the first and second logic potentials and to equalize both cores of all the master data lines to one of the two logic potentials. The columns of each area of the memory bank form at least two adjacent groups, each of which occupies a dedicated segment of the relevant area. Each local data line is assigned to exactly one segment of exactly one area of the memory bank, and each master data line is assigned to exactly one segment of each area of the memory bank. DRAM memories are a preferred, but not exclusive, field of application of the invention.
In digital data memories, the binary memory cells of each memory bank are often combined in a plurality of separate areas which each have a dedicated set of sense amplifiers, each of which is responsible for a subset of the cells of the relevant area. Usually, the cells of each memory area form a matrix of rows and columns, and each column is assigned a sense amplifier. Each sense amplifier is connected to all the cells of the relevant column via an assigned bit line. Each row can be addressed selectively by activation of an assigned word line. The corresponding activation signal is derived in a word line decoder (row decoder) from the row address of the memory cell to be read. The activation causes each cell of the relevant row to communicate its memory content via the bit line to the sense amplifier assigned to the relevant column, which sense amplifier thereupon generates an amplified signal representing the binary value of the stored datum. This representation, through the closing of a transfer switch individually assigned to the sense amplifier, is then transmitted to an assigned local data line, which can be connected via a line switch to an assigned master data line common to all the memory areas of the bank, in order to transmit the binary representation to a secondary sense amplifier and there to amplify it for the outputting of the datum.
The transfer switches are controlled by column selection signals that are derived by a column decoder from the column address of the memory cells to be read. The column selection signals are jointly fed to all the memory areas.
In many cases, particularly in large memory banks having a very high number of columns in each memory area, the total number n of columns of each area is divided into m adjacent groups, each of which contains k=n/m columns and occupies a corresponding segment of the memory area. Accordingly, the local data lines are also segmented. Each group (that is to say each segment) can in turn be divided into p adjacent subgroups, each of which contains q=k/p columns, in each case all the transfer switches assigned to the sense amplifiers of the same subgroup being driven by a common column selection signal assigned to the subgroup. In order that the data transmitted by the q transfer switches of the respective same subgroup are forwarded separately from one another in these cases, q local data lines are provided along each segment, each of which data lines is connected to exactly one individually assigned transfer switch of each subgroup of the columns of the relevant segment. If q=1, a dedicated column selection signal is generated for each column and thus for each transfer switch.
In accordance with the number m of segments, m bundles of master data lines are provided. Each of the bundles contains q master data lines that are assigned to the q local data lines of a respective segment of all the memory areas.
The bit lines, the local data lines and the master data line usually have two conductors or wires. For this purpose, each primary sense amplifier is configured with a symmetrical output. If the memory cell content that it senses corresponds to a datum of the first binary value, a potential difference whose polarity indicates the binary value of the datum stored in the cell appears at the output of the amplifier. If the cell content corresponds to a datum of the first binary value, then one output terminal of the amplifier goes to a first defined logic potential, and the other output terminal goes to a second defined logic potential. If the cell content corresponds to a datum of the second binary value, then the two logic potentials appear interchanged at the output terminals of the amplifier. Through the closing of the transfer switch with the line switch closed, the output potentials of the sense amplifier are applied to the cores of the assigned local data line and pass via the line switch to the lines of the assigned master data line in order to produce there a potential difference representing the sensed datum. The secondary sense amplifier is therefore configured as a differential amplifier with a symmetrical input. The supply potentials at the base and load ends of the amplifier are symmetrical with respect to the center between the two logic potentials and near one or the other logic potential.
In the quiescent state of the memory circuit, before a read or write mode is initiated, the lines of all the bit lines are equalized to a specific potential, which usually lies in the middle between the two logic potentials. The lines of all the local data lines are likewise equalized to this potential, specifically for the following reason: during the later column selection, the selected transfer switches are indeed closed not only in that memory area which contains the activated word line, but also in all the other memory areas whose bit lines have all maintained the equalization potential. The above-mentioned equalization of the local data lines to exactly this potential avoids unnecessary charging currents in these other memory areas.
In the quiescent state of the memory circuit, the lines of all the master data lines are likewise equalized to a specific potential. One of the two logic potentials is chosen for this second-mentioned equalization potential, specifically that logic potential which corresponds to or approaches the load-side supply potential of the secondary sense amplifiers. This is because the amplifier then remains in the linear region of the amplifier characteristic curve, if the input terminals are driven with the above-mentioned potential difference representing the sensed datum.
Each line switch has a control terminal for the application of a through-connect signal that closes the switch and keeps it closed for the duration of the signal. Before the closing of the line switches and before a transfer switch is closed at any of the primary sense amplifiers, the lines of all the bit lines and all the local data lines are disconnected from the source of their equalization potential; owing to their line capacitance, however, they still retain this potential for the time being.
In the case of memory circuits according to the prior art, all the line switches t
Fischer Helmut
Pfeiffer Johann
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
Tran Michael
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