Dram active termination control

DRAM architecture with combined sense amplifier pitch

DRAM array interchangeable between single-cell and twin-cell...

Dram bit line selection circuit for selecting multiple pairs of

DRAM core refresh with reduced spike current

Dram core refresh with reduced spike current

DRAM having a reduced chip size

DRAM implementation for more efficient use of silicon area

DRAM including an address space divided into individual blocks h

DRAM including an address space divided into individual...

DRAM interface circuit providing continuous access across...

DRAM memory system

Dram refresh circuit

DRAM with multiple virtual bank architecture for random row...

DRAM with segmental cell arrays and method of accessing same

DRAM with split word lines

Driver control circuit

Dual access memory array

Dual access memory array

Dual bank memory and systems using the same