Static information storage and retrieval – Addressing – Plural blocks or banks
Reissue Patent
2001-01-08
2002-12-10
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230010
Reissue Patent
active
RE037930
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention concerns a dynamic random-access memory (DRAM) with an address space divided into blocks, in which memory cells of individual blocks can be activated by a row address signal (RAS) delivered by a controller.
The address space of DRAMs are known to be divided into several blocks that are disposed physically in a row next to each other and logically in two rows next to each other. Viewed logically, two superimposed blocks of the two rows then form a single block. However, the access time for accessing data in the memory blocks is time consuming.
2. Summary of the Invention
It is accordingly an object of the invention to provide a DRAM that overcomes the above-mentioned disadvantages of the prior art devices of this general type, having a particularly short cycle time and thus permitting even more rapid data access.
With the foregoing and other objects in view there is provided, in accordance with the invention, a dynamic random-access memory (DRAM) having an address space divided into blocks, including: memory blocks having storage cells; a controller furnishing a row addressing signal (RAS); the memory blocks activated by activation signals derived from the row address signal and each of the memory blocks having an independent activation signal; and the activation signals for different memory blocks supplied in succession to the different memory blocks in a partial time overlap, so that an obtained data rate is increased as a result of partial simultaneous activation of at least two of the different memory blocks relative to an activation of only one memory block.
The task is solved in a DRAM according to the invention of the type mentioned at the outset, in that each individual block can be activated by an independent activation signal derived from the RAS signal. The activation signals for different blocks are supplied in succession in partial time overlap to the different blocks, so that the obtained data rate, as a result of partially simultaneous activation of at least two different blocks, is increased relative to the activation of only one block.
In the DRAM according to the invention, which, as further explained below, has a cycle time of about 60 ns and therefore is also referred to as a fast RAS cycle (FRC) DRAM one or more of the unactivated blocks can be activated before the activity of at least one previously selected block is completed. The cycle time of the RAS signal can thus be significantly shortened and reduced to about half. The shortening of cycle time is achieved, in particular, by a shorter precharging time in the RAS cycle.
If the ordinary longer precharging time is considered again, one can convert without difficulty from a normal mode of the existing DRAM to the FRC mode of the DRAM according to the invention. A “jump” between the normal mode and the FRC mode is therefore possible without a time loss.
Whereas, as explained above, an address restriction to 0.05% of the total address space is present in the FPM operation, the restriction is significantly lower in the FRC DRAM according to the invention: successive X addresses in the FRC DRAM according to the invention may not lie in the same storage block. Therefore, in a 4 M DRAM, after an X address that lies, say, in block
0
, blocks
1
to
3
are available (compare FIG.
1
), which means that 75% of the address space is freely available. In a 16 M DRAM this percentage of freely available addresses is even greater.
In the DRAM according to the invention the activation signals for the individual blocks are generated independently of each other. This can occur, for example, by deriving the beginning and end of an activation signal from the RAS signal. However, it is also possible to derive only the beginning of the activation signal from the RAS signal and then adjust the end of the activation signal by an internal timer. The restore timing is generated in the individual storage blocks, i.e., for these blocks individually, and not centrally, as previously done.
The same applies to the drive voltage and the decoder voltage of the word lines.
When a DRAM according to the invention has 4 independent blocks, i.e., a 4 M DRAM is present, a lower value X address can be used for block selection. The probability that two consecutive addresses lie in the same block can then be substantially reduced. Under practical conditions, a large number of addresses are accessed sequentially anyway, so that the addresses of the same block can scarcely occur in succession.
When the controller uses two different timings, which operate depending on the distance from the last access address, it is possible without difficulty for access to the same block to occur not in succession. The same can also be achieved by corresponding storage of an additional bit.
The DRAM according to the invention permits a cycle time gain in 4 blocks of about 55% of the cycle time of a normal DRAM during sequential access, 67% of the cycle time of a normal DRAM during statistical access and about 60% of the cycle time of a normal DRAM during practical use.
Since the activation signals in the DRAM according to the invention are derived from the RAS signal, a CAS-before-RAS mode is not possible.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a DRAM, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5097450 (1992-03-01), Toda et al.
patent: 5511030 (1996-04-01), Tanaka et al.
patent: 5528552 (1996-06-01), Kamisaki
patent: 5657285 (1997-08-01), Rao
patent: 5666322 (1997-09-01), Conkle
patent: 5699300 (1997-12-01), Akamatsu et al.
patent: 5991230 (1999-11-01), Urakawa
patent: 0 165 612 (1985-12-01), None
patent: 04-67389 (1992-03-01), None
Patent Abstracts of Japan No. 04-074378 (Kazuki), dated Mar. 9, 1992.
“System Memory Access Latency Reduction when Crossing Single in Line Memory Module/Dual in Line Memory Module Boundaries”, IBM Technical Disclosure Bulletin, vol. 39, No. 04, Apr. 1996, pp. 151-52.
“DRAM Vendors Juggle with new Architectures to Increase Performance”, Computer Design, Mar. 1995, pp. 71-86.
Elms Richard
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Phung Anh
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