Dram refresh circuit

Details Dram refresh circuit Dram refresh circuit

1995-12-01

1996-12-10

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

365236, 36518907, 365193, 365222, G11C 700, G11C 800

Patent

active

055838235

ABSTRACT:
A DRAM refresh circuit includes control logic for selectively placing the DRAM in normal modes of operation. An X register stores and outputs the capacity value of a DRAM, and a timer receives the output value of a timer register and a timer clock, and counts a refresh operation time. A refresh counter receives the output of a refresh counter register and a refresh counter clock, and counts the refresh operations. A comparator compares the output signals of the refresh counter, timer, and X register, and outputs a refresh enable signal in response to these signals. A priority circuit receives the output signals of the control logic and comparator and generates signals corresponding to the normal modes of operation and the refresh mode. A memory control signal generator is also provided for generating RASI and CASI signals and the refresh counter clock in accordance with the output from priority circuit.

REFERENCES:
patent: 4991112 (1991-02-01), Callemyn
patent: 5208782 (1993-05-01), Sakuta et al.
patent: 5502677 (1996-03-01), Takahashi

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