DRAM including an address space divided into individual blocks h

Static information storage and retrieval – Addressing – Plural blocks or banks

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36523001, G11C 800

Patent

active

06094398&

ABSTRACT:
A DRAM with an address space divided into blocks, in which storage cells of individual blocks can be activated by a row address signal (RAS) furnished by a controller. Each individual block can then be activated by an independent activation signal derived from the row address signal. The activation signals for different blocks are supplied to the different blocks in succession with a partial time overlap, so that the obtained data rate is increased relative to activation of only one block, owing to partial time activation of at least two different blocks.

REFERENCES:
patent: 5511030 (1996-04-01), Tanaka et al.
patent: 5528552 (1996-06-01), Kamisaki

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