Dual access memory array

Details Dual access memory array Dual access memory array

1999-01-06

2001-02-13

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230020, C365S230030

Reexamination Certificate

active

06188632

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to memory arrays in general and in particular, to dual access memory arrays which include cache memories.
BACKGROUND OF THE INVENTION
Memory arrays hold a plurality of words which often have to be accessed in order. Sometimes, for speed and space reasons, the memory is divided into two halves, as shown in
FIG. 1
to which reference is now briefly made. Each of the two halves, labeled
10
and
12
, have rows
14
therein in which data in the form of “words” are stored. The first four words, labeled
0
-
3
, are stored in the lowest row
14
al
of the left half
10
, the second four words, labeled
4
-
7
, are stored in lowest row
14
ar
of the right half
12
, the third four words, labeled
8
-
11
, are stored in row
14
bl
of the left half
10
, and the fourth four words, labeled
12
-
15
, are stored in row
14
br
, etc.
The memory array also includes a main controller
15
which converts an address of a word into associated row and column addresses, a line decoder
16
which selects the same row (
14
a
or
14
b
) of each of the two halves
10
and
12
as indicated by the main controller
15
, separate four-to-one multiplexers (MUX)
18
and
20
, each for reading data from their corresponding one of the two halves
10
and
12
, separate sense amplifiers
24
and
26
, a two-to-one MUX
22
for providing data from one of the two sense amplifiers
24
or
26
and an output buffer
23
. For writing data, the memory array includes two precharge and write buffer units
25
A and
25
B.
To access a word, the main controller
15
first determines which row and column the word is in. Main controller
15
then provides the row address to the line decoder
16
, the column address to the proper MUX
18
or
20
and a select signal to the 2:1 MUX
22
. The line decoder
16
, in turn, activates the word line, labeled
28
, connecting the eight words of a row
14
and the MUXs
18
,
20
and
22
select the relevant column holding the word of interest. For example, to read word
3
, line decoder
16
activates word line
28
a
, MUX
18
selects the relevant (i.e. the rightmost column) column and MUX
22
selects its left input (from sense amplifier
24
). To read word
4
, line decoder
16
activates word line
28
a
, MUX
20
selects the relevant column (i.e. the leftmost column) and MUX
22
selects its right input (from sense amplifier
26
). The output buffer
23
provides the data of MUX
22
as the output, labeled “DATA OUT”, of the memory array.
Some memories are read in order. To read first word
0
and then word
1
, the line decoder
16
has to activate word line
28
twice and MUX
18
has to select two different columns. Thus, two different read operations are required. Similarly, for any two words in the same row of one half
10
or
12
of the memory, two read operations are required. However, reading words
3
and
4
can be done in a single read operation, since the line decoder
16
has to activate the same word line, line
28
a
, and both of the MUXs
18
and
20
select their respective columns at the same time.
Unfortunately, not all adjacent words in the two halves can be read in a single operation. Adjacent words of different rows require separate read operations. For example, to read words
7
and
8
, requires a first read operation in which word line
28
a
is activated to read word
7
and then a second read operation in which word line
28
b
is activated to read word
8
Thus, for most neighboring words, consecutive read operations are required.
Similar access operations occur for writing data into the memory halves
10
and
12
. The main controller provides the row and column signals to the line decoder
16
and the MUXs
18
and
20
, respectively. At the same time, the data to be input, labeled “DATA IN”, is provided to the precharge and write buffer units
25
A and
25
B. Due to the access operations of the MUXs
18
and
20
and the line decoder
16
, the data will then be entered into the appropriate word.
U.S. Pat. No. 5,502,683 to Marchioro describes a dual ported memory which accesses multiple words in the memory array. To do so, it has word line switches at the boundaries of each word. When a switch is activated, it splits its row of words into left and right sections one of which is active and one of which is not. Furthermore, the switch connects the right section of its word line to the left section of the next adjacent word line. Thus, if the right section of a word line is activated, so will be the left section of the next adjacent word line. The data in the active sections is read.
SUMMARY OF THE PRESENT INVENTION
It is an object of the present invention to provide a memory array which enables any two consecutive words to be read in a single read operation.
There is therefore provided, in accordance with a preferred embodiment of the present invention, a memory array which includes a memory unit and a dual access controller. The memory unit stores a multiplicity of words and has a plurality of word lines each of which accesses a row of words. The memory unit is divided into a left memory unit and a right memory unit, each having generally half of the storage space of the memory unit, the left memory unit having left half word lines and the right memory unit having right half word lines. The dual access controller receives a word address N and a word separation amount S and activates the columns and half rows of the memory unit in which a main word and a second word S words from the main word are found. In one embodiment useful for neighboring words, the left memory unit holds the words with even addresses and the right memory unit holds the words with odd addresses. In another embodiment, the left memory unit holds the first four words of an eight word set and the right memory unit holds the second four words.
Additionally, in accordance with a preferred embodiment of the present invention, the dual access controller includes a multiple row main controller and a half row line decoder. The multiple row main controller receives the word address N and the word separation amount S and activates column and output multiplexers. It also determines the half row or rows on which the main and second words are found. The half row line decoder activates the half row or rows as indicated by the multiple row main controller.
There is also provided, in accordance with a preferred embodiment of the present invention, the half row line decoder which includes a line decoder, and even and odd half word line selectors. The line decoder is connected to the full word lines and activates the full word line N upon receipt of the word line address N. Each even half word line selector, which is associated with one even half word line, is connected between the line decoder and the associated even half word line. Similarly for the odd half word line selectors. Each odd half word line selector is connected to the even half word line selector of the row above the odd half word line selector and each even half word line selector is connected to the odd half word line selector of the row below the even half word line selector.
Finally, in accordance with a preferred embodiment of the present invention, the memory unit is one of the following types of memory units: read only memory, electrically programmable read only memory, electrically erasable programmable read only memory, and flash electrically erasable programmable read only memory.


REFERENCES:
patent: 4393472 (1983-07-01), Shimada et al.
patent: 4608672 (1986-08-01), Roberts et al.
patent: 4773048 (1988-09-01), Kai
patent: 5212780 (1993-05-01), Padgaonkar et al.
patent: 5293623 (1994-03-01), Froniewski et al.
patent: 5502683 (1996-03-01), Marchioro
patent: 5517457 (1996-05-01), Sakui et al.
patent: 5559990 (1996-09-01), Cheng et al.
patent: 5854770 (1998-12-01), Pascucci

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