DRAM memory system

Details DRAM memory system DRAM memory system

1996-12-26

1998-09-08

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 3652385, G11C 800

Patent

active

058055215

ABSTRACT:
A DRAM system having two data stored in continuous addresses that are fetched to improve the data transfer rate in a memory system. An output signal indicating shift up or shift down is added to a predecoder to supply to a decoder. The decoder receives this signal, and enables it to access a block higher or lower than a block corresponding to an address designated by the input address. Specifically, a line is arranged to a block adjacent to one block so that this line can be activated by a shift-up signal or the like.

REFERENCES:
patent: 5487050 (1996-01-01), Kim et al.
patent: 5513139 (1996-04-01), Butler
patent: 5574880 (1996-11-01), Shaw
patent: 5586080 (1996-12-01), Raad et al.
patent: 5610874 (1997-03-01), Park et al.

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