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Self-aligned contacts to gates

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
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Self-aligned contacts to gates

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned contacts to source/drain silicon electrodes utilizi

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
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Self-aligned copper interconnect architecture with enhanced copp

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
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Self-aligned copper interconnect structure and method of manufac

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
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Self-aligned copper plating/CMP process for RF lateral MOS...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
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Self-aligned copper silicide formation for improved...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
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Self-aligned cross point resistor memory array

Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
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Self-aligned cross point resistor memory array

Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
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Self-aligned damascene gate formation with low gate resistance

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned damascene gate with contact formation

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned damascene interconnect

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned deep trench DRAM array device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned deep trench isolation to shallow trench isolation

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
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Self-aligned dielectric cap

Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
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Self-aligned differential oxidation in trenches by ion...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned diffused source vertical transistors with deep tren

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned diffused source vertical transistors with stack cap

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned dog-bone structure for FinFET applications and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Self-aligned double gate mosfet with separate gates

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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