Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-10-29
2000-06-20
Chang, Joni
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438268, 438300, 438294, 438299, 438207, H01L 21336, H01L 218238
Patent
active
060777451
ABSTRACT:
A densely packed array of vertical semiconductor devices, having pillars with stack capacitors thereon, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped regions are self-aligned and are located below the pillars. The array has columns of bitlines and rows of wordlines. The lower doped regions of adjacent bitlines may be isolated from each other without increasing the cell size and allowing a minimum area of approximately 4 F.sup.2 to be maintained. The array is suitable for Gbit DRAM applications because the stack capacitors do not increase array area. The array may have an open bitline, a folded, or an open/folded architecture with dual wordlines, where two transistors are formed on top of each other in each trench. The lower regions may be initially implanted. Alternatively, the lower regions may be diffused below the pillars after forming thereof. In this case, the lower region diffusion may be controlled either to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.
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Burns, Jr. Stuart Mcallister
Hanafi Hussein Ibrahim
Kalter Howard Leo
Kocon Waldemar Walter
Welser Jeffrey J.
Berezny Neal
Chang Joni
International Business Machines - Corporation
Schecter Esq. Manny W.
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