Self-aligned damascene gate with contact formation

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S286000, C438S585000, C438S592000

Reexamination Certificate

active

06225170

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to gate formation and more specifically to a method of forming a self-aligned damascene gate with an attendant contact or contacts.
2. Description of the Related Art
Fabrication of an integrated circuit involves numerous processing steps. After impurity regions have been deposited within a semiconductor substrate and gate areas defined upon the substrate, interconnect routing is formed on the semiconductor topography and connected to contact areas to form an integrated circuit. The entire process of making an ohmic contact to the contact areas and routing interconnect material between ohmic contacts is described generically as “metalization”. This process, as is well known can involve electrically conductive materials other than metals per se. Nevertheless, as the complexity of integrated circuits has increased, the complexity of the metalization composition has also increased.
In such circuits, a junction is generally configured near a gate conductor within a substrate. Earlier contact structures involved depositing an interlevel dielectric over the junctions and gate conductors, and then etching an opening or window through the interlevel dielectric directly above the junctions to which contact is to be made. This etching, however, involved numerous problems. For example, the contact window opening required an additional masking step. Unfortunately, the mask is often times misaligned with the junction, resulting in an increase in junction capacitance. Additionally, opening a window of minimum size through a relatively thick interlevel dielectric is, by its nature, problematic. In order to achieve a relatively anisotropic etch, a plasma etch is required, leaving deleterious amounts of etch byproducts (e.g., polymers) at the base of the opening. Still further, difficulties arise whenever the interconnect material must extend over the interlevel dielectric and into the relatively small opening through the interlevel dielectric. Most conventional interconnect materials, such as aluminum, were unable to fill the openings without “cusping”, or without encountering step coverage at the juncture between the window and the interlevel dielectric surface.
More modem contact structures make use of contacts which are self-aligned with the junctions. More specifically, those contacts are referred to as self-aligned silicides, or so called “salicides”. A salicide process involves depositing a metal across the semiconductor topography, and then reacting the metal only in regions where silicon molecules are present. As a result of this reaction step, silicides form only at the upper surfaces of the junctions and the upper surfaces of the polysilicon gate conductors. A region between the junctions and the gate conductor upper surfaces is often provided with a sidewall spacer generally formed from silicon dioxide (oxide).
An interlevel dielectric is formed after the suicides are self-aligned to the silicon-bearing underlayers. This interlevel dielectric undergoes a patterned etch over the regions to which contact must be made. However, the pattern etch placement is not deemed as crucial as the etch needed to form a contact window in pre-salicide processes.
More specifically, the etch to the underlying salicide need only contact a portion of the salicide and need not be carefully bounded to the entire perimeter of the salicide. Another advantage to using a salicide, beyond its self-aligned properties, is the retained purity of the silicon-based material prior to silicide growth.
Silicide is grown upon and into the junctions without necessarily having to pre-clean those surfaces of interlevel dielectric etch byproducts commonly encountered in pre-salicide techniques.
Nevertheless, the techniques which are currently employed in prevailing art gate dielectric formations, gate deposition and patterning and contact formation are carried out sequentially. Accordingly, at high densities gate profile, contact misalignment and salicide bridging are all causes of performance and yield degradation.
SUMMARY OF THE INVENTION
The present invention is based on a method of forming a self-aligned damascene gate with an attendant contact or contacts which attenuates the above-mentioned problems through the use of a uniquely different fabrication process.
One embodiment of the present invention is such as to cover doped source and drain regions with a thick layer of a dielectric material, and then pattern and etch openings through the thick dielectric layer at locations which are selected with respect to the source and drain regions to be appropriate for gate and contact formation. Once the openings are formed, a layer of oxide (i.e. a Gox—gate oxide) is formed which covers the upper surface of the dielectric layer along with the side walls and the exposed substrate exposed at the bottom of the openings. Upon completion of this layer, a layer of polysilicon is formed over the oxide layer. This polysilicon layer is then doped and subjected to chemical-mechanical polishing (CMP) or the like to remove the polysilicon and oxide layers down to the level of the dielectric layer.
The site which is to become the gate is then masked. The exposed polysilicon and the oxide layer in the second opening are subsequently removed via suitable etching to expose the silicon of the semiconductor substrate. The mask is then removed and the exposed polysilicon and silicon surfaces are treated to form silicides.
The contact can then be filled and treated using CMP. Alternatively, the dielectric layer can be stripped off and the redeposited in a manner which permits contact formation in accordance with known techniques.
More specifically, a first aspect of the invention resides in a method of forming a semiconductor device having a gate and at least one contact, the method comprising the steps of: forming a thick dielectric layer over a semiconductor substrate in which a source region and a drain region are previously formed, said dielectric layer having a thickness of about 2000 Å to about 8000 Å; forming first and second openings in the dielectric layer at first and second sites which are respectively located with respect to the source and drain regions so that the first opening exposes part of both of the source region and the drain region and therefore is suited to the formation of a gate structure, and the second opening is located so as to expose only part of one of the source and drain regions; forming an oxide layer over the dielectric layer and over a side wall surface and a bottom of the first and second openings; forming a polysilicon layer over the oxide layer; doping the polysilicon layer; selectively removing portions of the polysilicon layer and the oxide layer until the dielectric layer is uncovered; masking the first site and removing the polysilicon and the oxide layers from the second opening to expose the semiconductor substrate at the bottom of the second opening; and then removing the mask and reacting the exposed portions of the polysilicon which remains in the first opening and the silicon at the bottom of the second opening to form first and second silicide layers.


REFERENCES:
patent: 3386016 (1968-05-01), Lindmayer
patent: 6090676 (2000-07-01), Gardner et al.
patent: 6093628 (2000-07-01), Lim et al.
patent: 6100142 (2000-08-01), Liao

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