Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1999-04-21
2000-10-31
Smith, Matthew
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438627, 438636, 438257, 438653, 438669, 438685, 257762, 257768, 257753, H01L 214763, H01L 2945
Patent
active
061402389
ABSTRACT:
A copper interconnect structure is formed in a semiconductor device using self-aligned copper or tungsten via pillars to connect upper and lower copper interconnect layers separated by a dielectric. The lower copper interconnect layer is formed on an underlying layer. The via pillars are formed on the lower copper interconnect layer. The copper upper interconnect layer is formed to make electrical contact to exposed upper surfaces of the via pillars.
REFERENCES:
patent: 4810332 (1989-03-01), Pan
patent: 4917759 (1990-04-01), Fisher et al.
patent: 5258096 (1993-11-01), Sandhu et al.
patent: 5354712 (1994-10-01), Ho et al.
patent: 5451543 (1995-09-01), Woo et al.
patent: 6030896 (2000-02-01), Brown
patent: 6037223 (2000-03-01), Su et al.
Anya Igwe U.
National Semiconductor Corporation
Smith Matthew
LandOfFree
Self-aligned copper interconnect structure and method of manufac does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Self-aligned copper interconnect structure and method of manufac, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-aligned copper interconnect structure and method of manufac will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2051199