Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-21
2001-12-11
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S584000, C438S585000, C438S586000, C438S652000, C438S655000, C438S657000
Reexamination Certificate
active
06329256
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to gate formation and more specifically to a method of forming a self-aligned damascene gate which enables the resistance of the gate to be reduced.
2. Description of the Related Art
Fabrication of an integrated circuit involves numerous processing steps. After impurity regions have been deposited within a semiconductor substrate and gate areas defined upon the substrate, interconnect routing is formed on the semiconductor topography and connected to contact areas to form an integrated circuit. The entire process of making an ohmic contact to the contact areas and routing interconnect material between ohmic contacts is described generically as “metallization”. This process, as is well known can involve electrically conductive materials other than metals per se. Nevertheless, as the complexity of integrated circuits has increased, the complexity of the metallization composition has also increased.
The impurity regions deposited within a semiconductor substrate are often referred to as junctions. A junction is generally configured near a gate conductor within a substrate. Earlier contact structures involved depositing an interlevel dielectric over the junctions and gate conductors, and then etching an opening or window through the interlevel dielectric directly above the junctions to which contact is to be made. This etching, however, involved numerous problems. For example, the contact window opening required an additional masking step. Unfortunately, the mask is often times misaligned with the junction, resulting in an increase in junction capacitance. Additionally, opening a window of minimum size through a relatively thick interlevel dielectric is, by its nature, problematic, in order to achieve a relatively anisotropic etch, a plasma etch is required, leaving deleterious amounts of etch byproducts (e.g., polymers) at the base of the opening. Still further, difficulties arise whenever the interconnect material must extend over the interlevel dielectric and into the relatively small opening through the interlevel dielectric. Most conventional interconnect materials, such as aluminum, were unable to fill the openings without “cusping”, or without encountering step coverage at the juncture between the window and the interlevel dielectric surface.
More modern contact structures make use of contacts which are self-aligned with the junctions. More specifically, those contacts are referred to as self-aligned suicides, or so called “salicides”. A salicide process involves depositing a metal across the semiconductor topography, and then reacting the metal only in regions where silicon molecules are present. As a result of this reaction step, silicides form only at the upper surfaces of the junctions and the upper surfaces of the polysilicon gate conductors. A region between the junctions and the gate conductor upper surfaces is often provided with a sidewall spacer generally formed from silicon dioxide (oxide).
An interlevel dielectric is formed after the suicides are self-aligned to the silicon-bearing underlayers. This interlevel dielectric undergoes a patterned etch over the regions to which contact must be made. However, the pattern etch placement is not deemed as crucial as the etch needed to form a contact window in pre-salicide processes.
More specifically, the etch to the underlying salicide need only contact a portion of the salicide and need not be carefully bounded to the entire perimeter of the salicide. Another advantage to using a salicide, beyond its self-aligned properties, is the retained purity of the silicon-based material prior to silicide growth. Silicide is grown upon and into the junctions without necessarily having to pre-clean those surfaces of interlevel dielectric etch byproducts commonly encountered in pre-salicide techniques.
Furthermore, the techniques which are currently employed in prevailing art gate dielectric formations, gate deposition and patterning and contact formation are carried out sequentially. Accordingly, at high densities gate profile, contact misalignment and salicide bridging are all causes of performance and yield degradation.
SUMMARY OF THE INVENTION
The present invention is based on a technique of forming a self-aligned damascene gate with an attendant contact or contacts which attenuates the above-mentioned problems through the use of a uniquely different fabrication process.
One embodiment of the present invention is such as to cover doped source and drain regions with a thick layer of a dielectric material, pattern and use a first etching technique to form an opening in the thick dielectric layer at locations which all but penetrates to the surface of the underlying semiconductor substrate. Following this a second WET etching technique is used to expose the surface of the substrate.
Following this, a layer of oxide is formed which covers the upper surface of the dielectric layer along with the side walls and the exposed substrate exposed at the bottom of the opening. Next, a layer of poly amorphous silicon is formed over the oxide layer. This layer however, is deposited only to the degree that a thickness which at most about ½ of the normal target thickness, is formed. This layer accordingly, is such that opening remains only partly filled and defines a void therein. This layer is then doped so as to act as a dopant reservoir.
Next, a layer of silicon rich tungsten silicide is deposited over the poly amorphous silicon layer. This layer fills the void left the polysilicon deposition. This is followed by polishing (e.g. chemical-mechanical-polishing (CMP)) to remove the superficial portions of the tungsten silicide layer, along with the portions of the dopedpolyamorphous silicon and oxide layers, down to the level of the dielectric layer.
At this stage, the plug-like remnants of the tungsten silicide layer which fills the void is cleaned and subsequently annealed. This heat treatment drives the excess silicon contained in the silicon rich tungsten silicide material, to the surface of the plug and to form a thin film having a thickness of about 500 Å. At the same time amorphous polysilicon is induced to undergo a change in crystal structure.
A contact mask is then formed. This covers the gate site and permits the dielectric thick layer to be etched out until the semiconductive silicon substrate is reached. The mask is then stripped and the exposed silicon at the bottom of the contact hole or holes and the silicon layer atop the salicide plug are then reacted for produce silicide layers and hence for a salicide.
The gate structure which is formed in this manner exhibits a significantly reduced resistance in the bulk of the gate material, excluding the salicide, is tungsten silicide which has a given suitable resistivity thus causing the gate resistance to be significantly reduced.
REFERENCES:
patent: 6090676 (2000-07-01), Gardner et al.
patent: 6093628 (2000-07-01), Lim et al.
patent: 6100142 (2000-08-01), Liao
patent: 6222240 (2001-04-01), Gardner et al.
patent: 6225170 (2001-05-01), Ibok et al.
Advanced Micro Devices , Inc.
Elms Richard
Owens Beth E.
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