Self-aligned damascene interconnect

Details Self-aligned damascene interconnect Self-aligned damascene interconnect

1999-04-19

2002-02-05

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S595000, C438S396000, C438S397000, C438S239000

Reexamination Certificate

active

06344389

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the multilevel interconnection of integrated circuit devices and more particularly to a DRAM device having a capacitorover-bitline (COB) structure wherein the capacitor contact is formed before the bitline to reduce circuit size and increase manufacturing efficiency.
2. Description of the Related Art
Generally, integrated circuits contain multilevel interconnection structures including wire levels and via contact levels which serve to route the flow of data, signal, and power throughout the chip. In the case of advanced high-density integrated circuit chips which contain a regular array of circuit features, such as a dynamic random access memory chip (DRAM), static random access memory (SRAM), or other programmable array devices, there can include arrays of features such as wires which are printed at a minimum pitch of lines and spaces. It may be advantageous and desirable to route an interconnection via which passes through the minimum-pitch array from a lower level to an upper level of wiring.
One example of a minimum pitch array of wires is a DRAM bitline level within a DRAM array which may include a storage device, such as a capacitor, a transistor controlling the flow of data to and from the storage device and a wordline for activating and deactivating the transistor. In addition, a capacitor contact may make electrical connection between the transistor and the capacitor and, similarly, a bitline contact may make electrical connection between the bitline and the transistor. In stacked DRAM technology, the capacitor can be located above or below the bitline. Structures which include the capacitor above the bitline are sometimes referred to as DRAM stacked capacitor-over-bitline (COB) devices.
Conventional DRAMs which include the capacitor below the bitline suffer from the disadvantage that the capacitor often shorts against the bitline contact. The capacitor-over-bitline structure is superior because it eliminates this type of defect.
With the capacitor-over-bitline structure, the capacitor contact is usually adjacent the bitline and can be separated from the bitline by insulating spacers. Conventional bitlines in capacitor-over-bitline structures are formed using common deposition, masking and etching techniques, such as reactive ion etching (RIE). Then the conventional processes form sidewall spacers along the bitline and subsequently form the capacitor contact adjacent the side wall spacers.
However, the sidewall spacers tend to limit the space available for the capacitor contact which decreases device performance and increases the defect rate as the devices are reduced in size. Essentially, the conventional processing for manufacturing a COB structure prohibits the device from being made smaller and, therefore, limits the device density of a given integrated circuit device. The conventional capacitor over-bitline structure may also provide separation between the capacitor contact and the bitline by increasing the spacing between these structures, and, hence increasing the overall area required for the chip. The present invention enables a compacting of overall chip area by providing a self-aligned interconnect structure which may be generally applicable to the fabrication of integrated circuits.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a structure and method for a self-aligned multi-level interconnect structure capacitor-over-bitline integrated circuit device comprising forming a field effect transistor on a substrate, forming a capacitor contact electrically connected to the field effect transistor, forming a bitline trench using the capacitor contact to align the bitline trench, forming insulating spacers in the bitline trench, forming a conductive bitline in the trench, the bitline being electrically connected to the field effect transistor, forming an inter-layer dielectric over the bitline, and forming a capacitor above the inter-layer dielectric, such that the capacitor is electrically connected to the capacitor contact.
The forming of the insulating spacers includes forming one of the insulating spacers on the capacitor contact. The forming of the capacitor contact includes forming a cap above the capacitor contact, wherein the cap protects the capacitor contact during the forming of the bitline trench and the cap aligns the bitline trench with the capacitor contact. The forming of the bitline comprises depositing a conductive material in the bitline trench using a damascene process.
A method of manufacturing a multilevel interconnection comprises forming a first wiring level, forming a first insulator over the first wiring level, forming a contact electrically connected to the first wiring level, forming a trench in the insulator using the to contact to align the trench, forming spacers in the trench, forming an intermediate wiring level in the trench, forming an insulator over the intermediate wiring level and forming a second wiring level above the insulator, such that the second wiring level is electrically connected to the contact.
The forming of the spacers includes forming one of the spacers on the contact. The forming of the contact includes forming a cap above the contact, wherein the cap protects the contact during the forming of the trench and the cap aligns the trench with the contact. The forming of the intermediate wiring level comprises depositing a conductive material in the trench using a damascene process. The size of the contact is unaffected by the spacers.
The invention enables the size reduction of the bitline wiring level spacing and prevents the capacitor contact from being reduced in size by the spacers. Therefore, the more critical capacitor contact size is not jeopardized and instead the less critical bitline size is slightly decreased. Thus, the invention allows a smaller stacked DRAM capacitorover-bitline structure to be manufactured, which allows for a higher density integrated circuit device, decreases manufacturing costs, decreases defects and increases efficiency.
Those skilled in the art will recognize that the structure and method described in this invention will have general applicability to the formation of multilevel interconnection integrated circuit devices, and not be limited to the DRAM and capacitorover bitline structure. The capacitor-over bitline structure described serves as an illustrative embodiment where the capacitor may be substituted for a wiring interconnection level.


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