Self-aligned copper interconnect architecture with enhanced copp

Details Self-aligned copper interconnect architecture with enhanced copp Self-aligned copper interconnect architecture with enhanced copp

1999-04-21

2000-02-29

Booth, Richard

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438627, 438636, 438639, 438648, 438653, 438669, 438685, 257762, H01L 214763, H01L 2144, H01L 2348

Patent

active

060308966

ABSTRACT:
A via is formed in a semiconductor device using a self-aligned copper-based pillar to connect upper and lower copper interconnect layers separated by a dielectric. The lower interconnect layer is formed on an underlying layer. The copper-based via pillar is formed on the lower interconnect layer. The upper interconnect layer is formed to make electrical contact to the exposed upper surface of the via pillar. Conductive diffusion barrier material is formed on vertical sidewalls of the lower interconnect layer.

REFERENCES:
patent: 4917759 (1990-04-01), Fisher et al.
patent: 5258096 (1993-11-01), Sandhu et al.
patent: 5451543 (1995-09-01), Woo et al.
patent: 5793112 (1998-08-01), Hasegawa et al.
patent: 5895265 (1999-04-01), Inoue et al.
patent: 5904565 (1999-05-01), Nguyen et al.

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