Delay-locked loop with reduced susceptibility to false lock
Delay-locked-loop (DLL) having symmetrical rising and falling cl
Delayed locked loop
Delayed locked loop (DLL)
Delayed Locked Loop Circuit
Delayed locked loop circuit
Delayed Locked Loop Circuit
Delayed locked loop clock generator using delay-pulse-delay...
Delayed locked loops and methods of driving the same
Delayed signal generation circuits and methods
Delayed-locked loop with fine and coarse control using...
Delta-sigma modulator clock dithering in a fractional-N...
Design structures including multiple reference frequency...
Design-for-test technique for a delay locked loop
Deskewing global clock skew using localized DLLs
Determining voltage level validity for a power-on reset...
Determining voltage level validity for a power-on reset...
Device and method for increasing the operating range of an...
Device and method for phase synchronization with the aid of...
Device and method for power-on/power-off checking of an...