Delta-sigma modulator clock dithering in a fractional-N...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Reexamination Certificate

active

07911247

ABSTRACT:
The clock signal supplied to the delta-sigma modulator in a fractional-N phase-locked loop is dithered. In one example, the PLL includes a novel programmable clock dithering circuit. The programmable clock dithering circuit is controllable via a serial bus to dither the phase of the clock signal in a selected one of several ways. If the clock signal is dithered in a first way (pseudo-random phase dithering), then the power of digital noise generated by the delta-sigma modulator is spread over a frequency band, thereby reducing the degree to which the noise interferes with other circuitry. If the clock signal is dithered in a second way (rotational phase dithering), then the power of digital noise is frequency shifted such that the degree to which the noise interferes with the other circuitry is reduced. The programmable clock dithering circuit can be controlled in other ways. For example, dithering can be programmably disabled.

REFERENCES:
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patent: 6606004 (2003-08-01), Staszewski et al.
patent: 2003/0137359 (2003-07-01), Patana
Perrott, Michael H. et al., “A 27-mW CMOS Fractional-N Synthesizer Using Digital Compensation for 2.5-Mb/s GFSK Modulation,” IEEE Journal of Solid-State Circuits, vol. 32, No. 12, Dec. 1997.
Galton, Ian, “Granular Quantization Noise in a Class of Delta-Sigma Modulators,” IEEE Transactions on Information Theory, vol. 40, No. 3, May 1994.
Damphousse, Simon et al., “All Digital Spread Spectrum Clock Generator for EMI Reduction,” ISSCC 2006, Session 14, Baseband and Channel Procession, 14.2, 2006 IEEE International Solid-State Circuits Conference.
Lee, Thomas H., “The Design of CMOS Radio-Frequency Integrated Circuits,” Cambridge University Press, pp. 519-521, 1998.

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