Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2006-05-16
2006-05-16
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S161000
Reexamination Certificate
active
07046058
ABSTRACT:
A delay-locked loop (DLL) circuit includes a phase interpolator circuit and variable delay circuit coupled in cascade and operative to generate an output clock signal that is delayed with respect to a reference clock signal responsive to respective first and second control signals applied to the phase interpolator and the variable delay circuit. The DLL circuit further includes a phase control circuit that generates the first and second control signals responsive to the output clock signal and the reference clock signal. The variable delay circuit may provide a coarser resolution than the phase interpolator circuit, for example, the variable delay circuit may include a tapped delay chain circuit configured to provide step changes in delay responsive to the second control signal. The phase control circuit may be operative to cause the phase interpolator circuit to shift from one extreme of a delay range thereof towards another extreme of the delay range concurrent with a step change in delay through the variable delay circuit to thereby limit overcompensation.
REFERENCES:
patent: 5485490 (1996-01-01), Leung et al.
patent: 5544203 (1996-08-01), Casasanta et al.
patent: 5604775 (1997-02-01), Saitoh et al.
patent: 5614855 (1997-03-01), Lee et al.
patent: 6125157 (2000-09-01), Donnelly et al.
patent: 6212126 (2001-04-01), Sakamoto
patent: 6281726 (2001-08-01), Miller, Jr.
patent: 6539072 (2003-03-01), Donnelly et al.
patent: 6836166 (2004-12-01), Lin et al.
patent: 2002/0015338 (2002-02-01), Lee
patent: 2002/0172314 (2002-11-01), Lin et al.
patent: 2002/0180501 (2002-12-01), Baker et al.
patent: 2003/0030473 (2003-02-01), Lee
patent: 2003/0085747 (2003-05-01), Hein et al.
patent: 2003/0167417 (2003-09-01), To et al.
patent: 2003/0182335 (2003-09-01), Conway et al.
patent: 2004/0066873 (2004-04-01), Cho et al.
patent: 2004/0158757 (2004-08-01), Lin
Lee et al., “A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM,” IEEE Journal of Solid-State Circuits, vol. 29, No. 12, Dec. 1994, pp. 1491-1496.
Pixel-Flow System Documentation, Rev. 0006.0, Chapter IV.9 Clock Input Buffer and Delay-Locked Loop (Jan. 23, 2001).
Efendovich et al., “Multifrequency Zero-Jitter Delay-Locked Loop,” IEEE Journal of Solid-State Circuits, vol. 29, No. 1, Jan. 1994, pp. 67-70.
Bazes, Mel, “An Interpolating Clock Synthesizer,” IEEE Journal of Solid-State Circuits, vol. 31, No. 9, Sep. 1996, pp. 1295-1301.
Lin et al., “A Register-Controlled Symmetrical DLL for Double-Data-Rate DRAM,” IEEE Journal of Solid-State Circuits, vol. 34, No. 4, Apr. 1999, pp. 565-568.
Garlepp et al, “A Portable Digital DLL for High-Speed CMOS Interface Circuits,” IEEE Journal of Solid-State Circuits, vol. 34, No. 5, May 1999, pp. 632-644.
Maneatis et al., “Precise Delay Generation Using Coupled Oscillators,” IEEE Journal of Solid-State Circuits, vol. 28, No. 12, Dec. 1993, pp. 1273-1282.
Sidiropoulos et al., “A Semidigital Dual Delay-Locked Loop,” IEEE Journal of Solid-State Circuits, vol. 32, No. 11, Nov. 1997, pp. 1683-1692.
Sidiropoulos et al., “SA 20.2: A Semi-Digital DLL with Unlimited Phase Shift Capability and 0.08-400MHz Operating Range,” 1997 IEEE International Solid-State Circuits Conference Proceedings, 10 pages.
Butka Brian
Fang Al
Farrell Mike
Integrated Device Technology, Ltd.
Lam Tuan T.
Myers Bigel & Sibley Sajovec, PA
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