Sampled delay locked loop insensitive to clock duty cycle
Sampling clock adjusting method, and an interface circuit...
Sampling phase detector for delay-locked loop
Sampling timebase system
Scalable integrated circuit architecture
Scalable integrated circuit architecture
Scalable integrated circuit architecture with analog circuits
Scalable integrated circuit architecture with analog circuits
Scheme for delay locked loop reset protection
Scheme to improve performance of timing recovery systems for...
Seamless coarse and fine delay structure for high...
Second order delay-locked loop for data recovery
Second order digital jitter attenuator
Segmented dual delay-locked loop for precise variable-phase cloc
Select signal generating circuit having clamp circuit for...
Selectable timing delay system
Selective restart circuit for an electronic device
Self calibrating digital delay-locked loop
Self-adjusting apparatus and a self-adjusting method for...
Self-aligned clock recovery circuit using a proportional...