Delayed signal generation circuits and methods

Details Delayed signal generation circuits and methods Delayed signal generation circuits and methods

2006-10-10

2006-10-10

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000

Reexamination Certificate

active

07119593

ABSTRACT:
Circuitry for delaying a signal includes a phase-locked loop comprising one or more output nodes for outputting one or more output signals in response to a reference signal. A buffer is coupled to the output nodes of the phase-locked loop for receiving phase-locked loop output signals and outputs one or more buffered output signals. A multiplexing element receives the buffered output signals and a control signal and generates an operative buffered output signal in response to the control signal. A delay line receives a delay control input signal and the operative buffered output signal from the multiplexing element. The delay line outputs a delayed output signal in response to the delay control input signal.

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patent: 2005/0162208 (2005-07-01), Zhang et al.
patent: 2006/0038596 (2006-02-01), Wang

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