Delay-locked loop with reduced susceptibility to false lock

Details Delay-locked loop with reduced susceptibility to false lock Delay-locked loop with reduced susceptibility to false lock

2007-05-22

2007-05-22

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

11201985

ABSTRACT:
A delay-locked loop (“DLL”) having reduced susceptibility to false lock. The DLL includes a delay path coupled to delay an input signal. The delay path includes two or more variable delay cells coupled in series and a feedback node coupled to an output of one of the variable delay cells. An inverter is coupled to receive the input signal and to output an inverted signal. A feedback circuit is coupled to receive the inverted signal from the inverter and to receive a feedback signal from the feedback node. The feedback circuit monitors a phase difference between the inverted signal and the feedback signal to generate a delay control signal in response to the phase difference to adjust a variable delay of the delay path.

REFERENCES:
patent: 5463337 (1995-10-01), Leonowich
patent: 6400197 (2002-06-01), Lai et al.
patent: 6466071 (2002-10-01), Kim et al.
patent: 2006/0029175 (2006-02-01), Schnarr

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