Delayed Locked Loop Circuit

Details Delayed Locked Loop Circuit Delayed Locked Loop Circuit

2008-07-29

2008-07-29

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000

Reexamination Certificate

active

07405603

ABSTRACT:
A Delayed Locked Loop Circuit of DLL comprises a buffer that receives a power-down signal and an inverted signal of a first clock signal; first and second delay lines an output device that outputs signals corresponding to the output signals of the first and second delay lines respectively; a replica delay unit, a phase comparator for comparing a phase difference between the output signal of the second buffer and the output signal of the replica delay unit; and a delay line controller for controlling delay times of the first delay line and the second delay line by corresponding to a comparison result of the phase comparator. The DLL circuit is configured such that the first and second buffers are disabled when the power-down mode entry notifying signal corresponding to a power-down mode is provided.

REFERENCES:
patent: 6914798 (2005-07-01), Kwon et al.
patent: 2007/0008024 (2007-01-01), Cheng
patent: 2007/0070731 (2007-03-01), Choi

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