Delayed locked loop

Details Delayed locked loop Delayed locked loop

2007-06-29

2009-12-15

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

07633323

ABSTRACT:
A delay locked loop is disclosed which includes a clock selector for selecting and outputting any one of normal-phase and reverse-phase external clocks in response to a clock selection information signal, a first delay line for delaying an output signal from the clock selector by a predetermined amount of time, a second delay line for delaying an inverted version of an output signal from the first delay line by a predetermined amount of time, and a phase mixer for mixing a phase of the output signal from the first delay line and a phase of an output signal from the second delay line and outputting an internal clock having a corrected duty cycle as a result of the mixing.

REFERENCES:
patent: 6518807 (2003-02-01), Cho
patent: 6677792 (2004-01-01), Kwak
patent: 6917229 (2005-07-01), Cho
patent: 7161397 (2007-01-01), Lee et al.
patent: 7282974 (2007-10-01), Lee
patent: 2006/0001463 (2006-01-01), Lee et al.
patent: 2007/0046347 (2007-03-01), Lee
patent: 1020040095981 (2004-11-01), None
patent: KO-10-2006-0000866 (2006-01-01), None

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