Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2002-07-16
2004-11-09
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S158000, C324S076530, C324S076540
Reexamination Certificate
active
06815986
ABSTRACT:
BACKGROUND OF INVENTION
As shown in
FIG. 1
, a typical computer system
10
has, among other components, a microprocessor
12
, one or more forms of memory
14
, integrated circuits
16
having specific functionalities, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another via communication paths
19
, e.g., wires, buses, etc., to accomplish the various tasks of the computer system
10
.
In order to properly accomplish such tasks, the computer system
10
relies on the basis of time to coordinate its various operations. To that end, a crystal oscillator
18
generates a system clock signal (referred to and known in the art as “reference clock” and shown in
FIG. 1
as SYS_CLK) to various parts of the computer system
10
. Modem microprocessors and other integrated circuits, however, are typically capable of operating at frequencies significantly higher than the system clock, and thus, it becomes important to ensure that operations involving the microprocessor
12
and the other components of the computer system
10
use a proper and accurate reference of time.
Accordingly, as the frequencies of modem computers continue to increase, the need to rapidly transmit data between circuit interfaces also increases. To accurately receive data, a clock signal is often transmitted to help recover data transmitted to a receiving circuit by some transmitting circuit. The clock signal determines when the data should be sampled by the receiving circuit. In some cases, the clock signal may change state at the beginning of the time the data is valid. However, this is typically undesirable because the receiving circuit operates better when the clock signal is detected during the middle of the time the data is valid. In other cases, the clock signal may degrade as it propagates from its transmission point. Such degradation may result from process, voltage, and/or temperature variations that directly or indirectly affect the clock signal. To guard against the adverse effects of poor and inaccurate clock signal transmission, a delay locked loop (“DLL”) is commonly used to generate a copy of the clock signal at a fixed phase shift with respect to the original clock signal.
FIG. 2
shows a portion of a typical computer system in which a DLL
30
is used. In
FIG. 2
, data
32
is transmitted from a transmitting circuit
34
to a receiving circuit
36
. To aid in the recovery of the data
32
by the receiving circuit
36
, a clock signal
38
is transmitted along with the data
32
. To ensure that the data
32
is properly latched by the receiving circuit
36
, the DLL
30
(which in
FIG. 2
is shown as being part of the receiving circuit
36
) regenerates the clock signal
38
to a valid voltage level and creates a phase shifted version of the clock signal
38
. Accordingly, the use of the DLL
30
in this fashion ensures (1) that the data
32
is properly latched by triggering the receiving circuit
36
at a point in time in which the data
32
is valid and (2) that the clock signal
38
is buffered by the receiving circuit
36
.
FIG. 3
shows a configuration of a typical DLL
40
. The DLL
40
includes a cascade of two loops. The first loop
42
includes a voltage-controlled delay line
44
, composed of several delay elements
46
, that inputs a reference clock, ref_elk
48
, and outputs an output clock, out_elk
50
, that is shifted 180 degrees from the reference clock
48
. A delay of the voltage-controlled delay line
44
is controlled by a feedback system including a phase detector
52
, a charge pump
54
, and a bias generator
56
. The phase detector
52
detects any phase offset between the reference clock
48
and the output clock
50
and generates UP
58
and DOWN
60
pulses that control the charge pump
54
. Depending on the UP
58
and DOWN
60
pulses, the charge pump
54
transfers charge to or from a filter capacitor
62
, thereby generating a control voltage, V
ctrl
64
. The bias generator
56
inputs the control voltage
64
and produces bias voltages V
cn
66
and V
cp
68
that adjust the delay of the delay elements
46
in the voltage-controlled delay line
44
such that the delay of the voltage-controlled delay line
44
is proportional to a phase shift of 180 degrees from the reference clock
48
.
The second loop
45
is an ‘interpolating’ loop that takes the outputs of the delay elements
46
in the voltage-controlled delay line
44
and produces an interpolated clock signal that is locked in phase, i.e., 0 degrees phase offset, with the reference clock
48
. This is accomplished through a plurality of stages. A first group of clock signal from a pair of successive delay elements
46
are selected by an analog multiplexer known as a ‘phase selector’
70
. The selected delay element
46
outputs are then inverted by a phase inverter
72
is required. A phase interpolator
74
then interpolates between the output pair of clock signals from the phase inverter
72
, thereby generating a clock signal that is places between the phase inverter
72
outputs. The output from the phase interpolator
74
is then compared to the reference clock
48
using a digital phase detector
76
. The digital phase detector
76
detects the phase offset between the interpolated clock signal and the reference clock
48
, and its output serves as an input to a finite state machine
78
that adjusts (1) interpolating weights in the phase interpolator
74
, (2) select signals in the phase selector
70
, and (3) the phase inversion in the phase inverter
72
.
The use of DLLs, such as the one described above with reference to
FIG. 3
, is becoming increasingly important with the advent of modern high-speed high-bandwidth processors. Additionally, because a DLL typically occupies a significant amount of integrated circuit space, DLL implementation is becoming a significant concern for circuit designers and the like.
SUMMARY OF INVENTION
According to one aspect of the present invention, an integrated circuit having a delay locked loop comprises: a phase detector that inputs a reference clock signal and an output clock signal from the delay locked loop; a charge pump, responsive to an output from the phase detector, that outputs a control voltage signal; a bias generator that generates at least one bias signal dependent on the control voltage signal; a voltage-controlled delay line, responsive to the at least one bias signal, that outputs the output clock signal, where the voltage-controlled delay line comprises a plurality of delay elements that each comprise an NMOS device and a PMOS device; a first plurality of design-for-test devices positioned at inputs to NMOS devices in the plurality of delay elements; and a second plurality of design-for-test devices positioned at inputs to PMOS devices in the plurality of delay elements.
According to another aspect, an integrated circuit having a delay locked loop comprises: means for inputting a reference clock signal and an output clock signal from the delay locked loop; means for outputting a control voltage signal dependent on the means for inputting the reference clock signal and the output clock signal; means for generating at least one bias signal dependent on the control voltage signal; means for outputting the output clock signal dependent on the at least bias signal, where the means for outputting the output clock signal comprises a plurality of delay elements that each comprise an NMOS device and a PMOS device; first testing means for testing the delay locked loop, where the first testing means is positioned at inputs to NMOS devices in the plurality of delay elements; and second testing means for testing the delay locked loop, where the second testing means is positioned at inputs to PMOS devices in the plurality of delay elements.
According to another aspect, a method for manufacturing a delay locked loop comprises: operatively connecting a phase detector that is arranged to input a reference clock signal and an output clock signal from the delay locked loop to
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