Delayed locked loops and methods of driving the same

Details Delayed locked loops and methods of driving the same Delayed locked loops and methods of driving the same

2006-05-16

2006-05-16

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

07046061

ABSTRACT:
Disclosed are a delay locked loop (DLL) and a method of driving the same. The delay locked loop includes a clock buffer for buffering an inputted external clock to generate an internal clock, the clock buffer generating a control signal for disabling the internal clock depending on whether the power is down, a delayed line for delaying the internal clock, a clock driver for buffering the output of the delayed line to generate a clock signal, the clock driver disabling the clock signal depending on whether the power is down, a delay monitor for delaying the external clock, a phase detector for detecting the difference in a phase between the internal clock and the output of the delayed monitor to generate a detected signal, the phase detector being disabled according to the control signal, and a shift register for controlling the delayed line according to the detected signal from the phase detector. Therefore, it is possible to sufficiently satisfy power down excitation time while reducing current consumption of the entire semiconductor device during the power down state.

REFERENCES:
patent: 6525595 (2003-02-01), Oku
patent: 6545941 (2003-04-01), Kato et al.
patent: 6693474 (2004-02-01), Kim
patent: 6759911 (2004-07-01), Gomm et al.

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