Deskewing global clock skew using localized DLLs

Details Deskewing global clock skew using localized DLLs Deskewing global clock skew using localized DLLs

2001-10-11

2004-02-03

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000

Reexamination Certificate

active

06686785

ABSTRACT:

BACKGROUND OF INVENTION
A typical computer system includes at least a microprocessor and some form of memory. The microprocessor has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions necessary for the operation and use of the computer system.
FIG. 1
shows a typical computer system (
10
) having a microprocessor (
12
), memory (
14
), integrated circuits (
16
) that have various functionalities, and communication paths (
18
), i.e., buses and wires, that are necessary for the transfer of data among the aforementioned components of the computer system (
10
).
The components of a computer system use a reference of time to perform the various operations of the computer system. This reference of time is provided to the components of the computer system using one or more clock signals. The components use the one or more clock signals to determine when to conduct certain operations. As computer systems continue to operate at ever-increasing frequencies, it becomes more and more important to ensure that the components of a computer system receive their clock signals in an accurate and timely manner because a mistiming has the potential to cause an error, performance setback, or an outright malfunction of the computer system.
FIG. 2
shows a clock distribution network (
20
) for a microprocessor (
12
). A reference clock (also known in the art as “system clock” and shown in
FIG. 2
as REF_CLK), which is typically generated from outside the microprocessor (
12
), serves as an input to a phase locked loop (“PLL”) (
15
). Essentially, the PLL (
15
) uses feedback to maintain a specific phase relationship between its output (shown in
FIG. 2
as CHIP_CLK) and the reference signal. The chip clock from the PLL (
15
) is then distributed to one or more clock drivers/buffers (
17
), which, in turn, distribute the chip clock to a global clock grid (
19
), where the global clock grid (
19
) feeds the chip clock to various microprocessor components such as local clock grids (
24
) and a feedback loop (
26
) that feeds the chip clock back to the PLL (
14
). The local clock grids (
24
) feed the chip clock to base components of the microprocessor (
12
), such as latches (
22
) and flip-flops (
28
).
As a clock signal, such as the chip clock shown in
FIG. 2
, is propagated to the various parts and components of a microprocessor, one or more types of system variations may alter the behavior and/or integrity of the clock signal. Common system variations include, but are not limited to, power variations, temperature variations, and process variations. Due to these and other variations across a microprocessor, a particular clock signal may arrive at different parts of the microprocessor at different times. This difference in the arrival of a clock signal at different system components is referred to and known in the art as “clock skew.”
As partly discussed above, clock skew is a function of architectural factors such as load, device distribution across a microprocessor, device mismatch, and temperature and voltage gradients across the microprocessor. By designing a microprocessor that accounts for some of these variations, the amount of clock skew in the microprocessor may be reduced. The process of removing or decreasing clock skew is referred to and known in the art as “deskewing.”
Clock deskewing is typically performed in an upper distribution layer of a clock distribution network. For example, in a clock distribution network that has a global and a local layer, deskewing is performed in the global layer. Similarly, in a network that has a global, a regional, and a local layer, deskewing is performed in the global and/or regional layers.
FIG. 3
shows a typical clock distribution network (
40
) having a global distribution layer (
42
), a regional distribution layer (
44
), a local distribution layer (
46
), where clock deskewing occurs in the regional distribution layer (
44
). In
FIG. 3
, a PLL (
48
) distributes a chip clock to a set of one or more clock drivers/buffers (
50
), which, in turn output the chip clock to a set of deskewing buffers (
52
) in the regional distribution layer (
44
). The deskewing buffers (
52
) deskew the chip clock and then distribute the deskewed chip clock to a global clock grid (
54
), which is connected to one or more local clock grids (
58
), where the local clock grids (
58
) are connected to microprocessor components such as latches (
56
), flip-flops (
60
), and other types of circuit elements (not shown).
A deskewing buffers, as shown in
FIG. 3
are typically implemented as a delay locked loop (DLL). A DLL is a component that uses a control signal to maintain an output signal in a specific delay relationship with an input signal. The control signal indicates to the DLL how much delay, if any, the DLL needs to insert into the output signal. Because the amount of delay a DLL inserts is typically not a constant or predefined value, the DLL is known as a “variable delay circuit.”
As shown in
FIG. 3
, when deskewing buffers are included in the regional distribution layer of a clock distribution network, adjusting global clock skew is a less onerous task. However, such deskewing does not account for clock skew contributed by devices and variations in the local distribution layer (such clock skew is referred to and known in the art as “localized clock skew”).
SUMMARY OF INVENTION
According to one aspect of the present invention, an integrated circuit comprise: a delay locked loop; a clock delay circuit comprising at least one tunable buffer arranged to output a clock signal to a portion of a clock grid disposed on the integrated circuit; a first phase detector associated with the clock delay circuit and arranged to input a reference clock signal and a feedback signal from the portion of the clock grid, where the first phase detector is arranged to output a signal to the clock delay circuit dependent on a phase difference between the reference clock signal and the feedback signal, and where the reference clock signal is connected to one of an output of the delay looked loop and another portion of the clock grid; and a second phase detector not associated with the clock delay circuit and having a reference clock signal input operatively connected to the portion of the clock grid.
According to another aspect, a method for decreasing clock skew comprises: comparing a phase difference between a reference clock signal and a feedback signal; responsive to the phase difference between the reference clock signal and the feedback signal, adjusting a delay of a first clock delay circuit operatively connected to a portion of a clock grid, where the feedback signal is operatively connected to the portion of the clock grid; comparing a nhase difference between the feedback signal and another feedback signal, where the another feedback signal is operatively connected to another portion of the clock arid: and responsive to the phase difference between the feedback signal and the another feedback signal, adjusting a delay of a second clock delay circuit operatively connected to the another portion of the clock grid.
According to another aspect, an integrated circuit comprises: means for comparing a phase difference between a reference clock signal and a feedback signal; means for adjusting a delay of a first clock delay circuit operatively connected to a portion of a clock grid dependent on the means for comparing the phase difference between the reference clock signal and the feedback signal, where the feedback signal is operatively connected to the portion of the clock grid; means for comparing a phase difference between the feedback signal and another feedback signal, where the another feedback signal is operatively connected to another portion of the clock mid: and means for adjusting a delay of a second clock delay circuit operatively connected to the another portion of the clock grid dependent on the means for comparing the phase difference between the feedback signal and the another feedback signal.
Other aspects a

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