Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-03-15
2002-12-31
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S151000, C327S048000
Reexamination Certificate
active
06501310
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sampling clock adjusting method for generating a digital image signal using an analog image signal. The present invention also relates to an interface circuit for adjusting a sampling clock.
2. Description of the Related Art
Recently, digital display devices, such as a liquid crystal display and the like have been commonly used. For example, liquid crystal displays have become widely used instead of CRT (Cathode Ray Tube) displays and the like, as the display of computers.
In the case where a digital display device is used instead of an analog display device, an analog image signal should be converted to a digital image signal by sampling the analog image signal at predetermined intervals.
Since a device for generating an image signal generates an analog image signal by using an internal video clock, the level of the image signal changes according to the cycle of this video clock. Due to this, at the time of sampling an analog image signal, the sampling needs to be conducted according to a cycle which is the same as the cycle of the video clock. Further, if the sampling is conducted in an area where the level of the image signal is unstable, a noise might occur in the image to be displayed. Due to this, the sampling of the image signal needs to be conducted in an area where the level of the image signal is stable.
FIG. 10
is a block diagram showing one example of the interface circuit for generating a signal for sampling (sampling clock).
The interface circuit receives an analog image signal
101
, a horizontal synchronizing signal
105
and a vertical synchronizing signal
109
supplied from an image signal output device (not shown), such as a computer etc., then, the interface circuit outputs the image signal
101
, a regenerative horizontal synchronizing signal
106
and a sampling clock
108
to a digital display device
9
.
As shown in
FIG. 10
, the interface circuit comprises a PLL (Phase Lock Loop) circuit
4
, an MPU (Micro Processing Unit)
5
and a delay circuit
6
.
As shown in
FIG. 11
, the PLL circuit
4
comprises a phase detector
21
, a LPF (Low Pass Filter)
22
, a VCO (Voltage Controlled Oscillator)
23
and a frequency divider
24
.
The PLL circuit
4
generates the regenerative horizontal synchronizing signal
106
having a frequency F equal to that of the horizontal synchronizing signal
105
and a base clock
107
having a frequency N·F which is N times as large as that of the horizontal synchronizing signal
105
, from the horizontal synchronizing signal
105
.
The regenerative horizontal synchronizing signal
106
is supplied from the PLL circuit
4
directly to the display device
9
. The base clock
107
is supplied to the display device
9
as the sampling clock
108
after the phase thereof is delayed by the delay circuit
6
.
The display device
9
samples the image signal
101
by using the regenerative horizontal synchronizing signal
106
and the sampling clock
108
which are supplied from the interface circuit, and converts the analog image signal into a digital image signal Then, the display device
9
displays a predetermined image with the digital image signal.
In the case where the image is not displayed desirably as a result of the interference of a noise and the like, the frequency and phase of the sampling clock
108
are adjusted by adjusting the dividing value of the frequency divider
24
, and the delay amount of the delay circuit
6
. Specifically, the frequency of the sampling clock
108
is set equal to the frequency of the video clock in the device for generating the image signal
101
, and the phase of the sampling clock
108
is adjusted so that the image signal
101
can be sampled in an area where the level of the image signal
101
is stable.
In the case where the interface circuit having the structure shown in
FIG. 10
is used, the dividing value of the frequency divider
24
and the delay amount of the delay circuit
6
are manually adjusted. Specifically, a operator of the display device
9
operates predetermined buttons and dials while watching the image displayed on the display device
9
. Due to this, signals indicating the dividing value and the delay amount, respectively, are input in the MPU
5
. The MPU
5
adjusts the frequency and phase of the sampling clock
108
by setting the dividing value of the frequency divider
24
and the delay amount of the delay circuit
6
in accordance with the input signals.
However, manual adjustment of the dividing value and the delay amount is troublesome and requires a high level of skill and experience. Therefore, an interface circuit which automatically adjusts the dividing value and the delay amount has been proposed.
FIG. 12
is a block diagram showing one example of an interface circuit which automatically adjusts the frequency and phase of the sampling clock
108
.
As shown in
FIG. 12
, the interface circuit which automatically adjusts the sampling clock
108
comprises a clamping circuit
1
, a D/A converter
2
, a comparator
3
, and a measuring circuit
8
in addition to the structure of the interface circuit shown in FIG.
10
.
The analog image signal
101
supplied from the image signal output device is generally a signal having an amplitude of 0.7 volt and does not contain any direct-current component. The clamping circuit
1
clamps the image signal
101
at a reference potential by adding a predetermined direct current voltage to the image signal
101
, and outputs the image signal
101
as an image signal
102
to the comparator
3
.
The comparator
3
determines whether or not there are predetermined data, based on the level of the image signal
102
. Specifically, the comparator
3
determines whether or not there are predetermined data in accordance with whether the level of the image signal
102
is higher or lower than the level of the reference voltage
103
supplied from the MPU
5
via the D/A converter
2
. Then, the comparator
3
outputs the data existence signal
104
representing the determination result into the measuring circuit
8
.
As described above, the PLL circuit
4
generates the regenerative horizontal synchronizing signal
106
and the base clock
107
from the horizontal synchronizing signal
105
. The regenerative horizontal synchronizing signal
106
is supplied from the PLL circuit
4
directly to the measuring circuit
8
and the display device
9
. The base clock
107
is supplied from the PLL circuit
4
to the measuring circuit
8
and the display device
9
as the sampling clock
108
after the phase thereof is delayed by the delay circuit
6
.
The measuring circuit
8
counts numbers of pulses of the sampling clock
108
supplied from the delay circuit
6
, using the data existence signal
104
supplied from the comparator
3
and the regenerative horizontal synchronizing signal
106
supplied from the PLL circuit
4
.
Specifically, as shown in
FIG. 13
, the measuring circuit
2
counts a number HD
min
of pulses of the sampling clock
108
and a number HD
max
of pulses of the sampling clock
108
during every one horizontal synchronization period (scanning period) which is a period since one fall until the next fall of the regenerative horizontal synchronizing signal
106
.
The number HD
min
is a number of pulses which are counted since the first fall of the regenerative horizontal synchronizing signal
106
until the first rise of the data existence signal
104
during the scanning period. The number HD
max
is a number of pulses which are counted since the first fall of the regenerative horizontal synchronizing signal
106
and the final fall of the data existence signal
104
.
Then, the measuring circuit
8
outputs measurement result signal
111
indicating the respective numbers HD
min
and HD
max
, one after another into the MPU
5
.
The MPU
5
previously stores a program for adjusting the frequency and phase of the sampling clock
108
, information regarding resolutions of analog image signals, and the like.
First, the MPU
Cox Cassandra
McGinn & Gibb PLLC
Wells Kenneth B.
LandOfFree
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