Sampling phase detector for delay-locked loop

Details Sampling phase detector for delay-locked loop Sampling phase detector for delay-locked loop

2007-02-06

2007-02-06

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000

Reexamination Certificate

active

11103527

ABSTRACT:
A delay-locked loop (DLL) architecture is provided that includes a voltage controlled delay line, a sample-and-hold circuit and an amplifier circuit. The voltage controlled delay line may have a plurality of buffer stages to provide a first clock signal and a second clock signal. The sample-and-hold circuit may receive signals corresponding to the first clock signal and the second clock signal. The sample-and-hold circuit may provide two sampled signals based on the received signals. Additionally, the amplifier circuit may be coupled to the sample-and-hold circuit and the voltage controlled delay line. The amplifier circuit may provide a control voltage to the buffer stages of the voltage controlled delay line based on the sampled signals received from the sample-and-hold circuit.

REFERENCES:
patent: 6424193 (2002-07-01), Hwang
patent: 7034591 (2006-04-01), Wang
“A Semidigital Dual Delay-Locked Loop”, Stefanos Sidiropoulos, et al. , IEEE Journal of Solid-State Circuits, vol. 32, No. 11, Nov. 1997.
“Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, John G. Maneatis, IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996.
“3.3V, 1.6 GHz, Low-Jitter, Self-Correcting DLL Based Clock Synthesizer in 0.5μm CMOS.”, David J. Foley, et al., , ISCA 2000-IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland.

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